Patents by Inventor Petar B. Atanakovic

Petar B. Atanakovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7968384
    Abstract: A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: June 28, 2011
    Inventors: Petar B. Atanakovic, Michael Lebby
  • Patent number: 7863139
    Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: January 4, 2011
    Inventor: Petar B. Atanakovic
  • Patent number: 7825470
    Abstract: A method of fabricating semiconductor components in-situ and in a continuous integrated sequence includes the steps of providing a single crystal semiconductor substrate, epitaxially growing a first layer of rare earth insulator material on the semiconductor substrate, epitaxially growing a first layer of semiconductor material on the first layer of rare earth insulator material, epitaxially growing a second layer of rare earth insulator material on the first layer of semiconductor material, and epitaxially growing a second layer of semiconductor material on the second layer of rare earth insulator material. The first layer of rare earth insulator material, the first layer of semiconductor material, the second layer of rare earth insulator material, and the second layer of semiconductor material form an in-situ grown structure of overlying layers. The in-situ grown structure is etched to define a semiconductor component and electrical contacts are deposited on the semiconductor component.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: November 2, 2010
    Inventor: Petar B. Atanakovic
  • Publication number: 20100068858
    Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.
    Type: Application
    Filed: November 25, 2009
    Publication date: March 18, 2010
    Applicant: TRANSLUCENT INC.
    Inventor: Petar B. Atanakovic
  • Patent number: 7646066
    Abstract: A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulating material, an active layer of crystalline semiconductor material, an upper gate insulating layer of crystalline rare earth insulating material, and an upper gate layer of crystalline rare earth conductive material. The upper gate layer and the upper gate electrically insulating layer are etched and a contact is deposited on the upper gate layer to define an upper gate structure. An impurity is implanted into the lower gate layer to define a lower gate area aligned with the upper gate structure. A source and drain are formed in the active layer and contacts are deposited on the source and drain, respectively.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: January 12, 2010
    Assignee: Translucent, Inc.
    Inventor: Petar B. Atanakovic
  • Patent number: 7586177
    Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: September 8, 2009
    Assignee: Translucent, Inc.
    Inventor: Petar B. Atanakovic
  • Patent number: 7538016
    Abstract: The present invention describes a method including the steps of providing a single crystal semiconductor substrate, forming a layer of rare earth silicide on a surface of the semiconductor substrate, forming a first layer of insulating material on the layer of rare earth silicide, forming a layer of electrically conductive material on the first layer of insulating material, and forming a second layer of insulating material on the layer of electrically conductive material. In one embodiment the step of forming the layer of rare earth silicide includes depositing a layer of rare earth metal on a surface of the semiconductor substrate depositing a layer of insulating material on the layer of rare earth metal, and annealing the structure to form a layer of rare earth silicide in conjunction with the surface of the semiconductor substrate and a rare earth doped insulating layer in conjunction with the layer of insulating material.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 26, 2009
    Assignee: Translucent, Inc.
    Inventors: Petar B. Atanakovic, Michael Lebby
  • Patent number: 7416959
    Abstract: A method of fabricating a semiconductor-on-insulator semiconductor substrate is disclosed that includes providing first and second semiconductor substrates. Either oxygen or nitrogen is introduced into a region adjacent the surface of the first semiconductor substrate and a rare earth and hydrogen are implanted at different energy levels into the second semiconductor substrate to produce a rare earth rich region adjacent the surface and a hydrogen layer spaced from the surface. The surface of the first semiconductor substrate is bonded to the surface of the second semiconductor substrate in a process that includes annealing to react either the oxygen or the nitrogen with the rare earth to form an interfacial insulating layer of either rare earth oxide or rare earth nitride. During the anneal the hydrogen layer is blistered and a portion of the second semiconductor substrate is removed and the surface polished to form a thin crystalline active layer on the interfacial insulating layer.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: August 26, 2008
    Assignee: Translucent Inc.
    Inventor: Petar B. Atanakovic