Patents by Inventor Pete D. Vogt
Pete D. Vogt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379625Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Applicant: Tahoe Research, Ltd.Inventors: Pete D. VOGT, Andre SCHAEFER, Warren MORROW, John B. HALBERT, Jin KIM, Kenneth D. SHOEMAKER
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Patent number: 12046577Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: GrantFiled: May 28, 2019Date of Patent: July 23, 2024Assignee: Tahoe Research, Ltd.Inventors: Pete D. Vogt, Andre Schaefer, Warren Morrow, John B. Halbert, Jin Kim, Kenneth D. Shoemaker
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Patent number: 10599592Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.Type: GrantFiled: February 22, 2019Date of Patent: March 24, 2020Assignee: Intel CorporationInventors: Bruce Querbach, Pete D. Vogt
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Patent number: 10592445Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.Type: GrantFiled: December 3, 2018Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Bill Nale, Christopher E. Cox, Kuljit S. Bains, George Vergis, James A. McCall, Chong J. Zhao, Suneeta Sah, Pete D. Vogt, John R. Goles
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Patent number: 10509738Abstract: An extension of node architecture and proxy requests enables a node to expose memory computation capability to remote nodes. A remote node can request execution of an operation by a remote memory computation resource, and the remote memory computation resource can execute the request locally and return the results of the computation. The node includes processing resources, a fabric interface, and a memory subsystem including a memory computation resource. The local execution of the request by the memory computation resource can reduce latency and bandwidth concerns typical with remote requests.Type: GrantFiled: July 1, 2016Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Narayan Ranganathan, Pete D. Vogt
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Publication number: 20190304953Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: ApplicationFiled: May 28, 2019Publication date: October 3, 2019Inventors: Pete D. VOGT, Andre SCHAEFER, Warren MORROW, John B. HALBERT, Jin KIM, Kenneth D. SHOEMAKER
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Publication number: 20190258594Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.Type: ApplicationFiled: February 22, 2019Publication date: August 22, 2019Inventors: Bruce QUERBACH, Pete D. VOGT
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Publication number: 20190213148Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.Type: ApplicationFiled: December 3, 2018Publication date: July 11, 2019Inventors: Bill NALE, Christopher E. COX, Kuljit S. BAINS, George VERGIS, James A. McCALL, Chong J. ZHAO, Suneeta SAH, Pete D. VOGT, John R. GOLES
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Patent number: 10339072Abstract: A system with memory includes a repeater architecture where the memory connects to a host with one bandwidth, and a repeater extends a channel with a lower bandwidth. A memory circuit includes a first group of memory devices coupled point-to-point to a host device via a first group of read signal lines. The memory circuit includes a second group of memory devices coupled point-to-point to the first group of memory devices second group of read signal lines to extend the memory channel to the second group of memory devices. The second group of read signal lines has fewer read signal lines than the first group. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.Type: GrantFiled: April 1, 2016Date of Patent: July 2, 2019Assignee: Intel CorporationInventors: Bill Nale, Pete D Vogt
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Patent number: 10249597Abstract: Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package includes a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSV s) formed through the one or more memory dies; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; and a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV.Type: GrantFiled: September 30, 2016Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Lakshminarayana Pappu, Kalyan C. Kolluru, Pete D. Vogt, Christopher J. Nelson, Amande B. Trang, Uddalak Bhattacharya
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Patent number: 10242717Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.Type: GrantFiled: November 9, 2017Date of Patent: March 26, 2019Assignee: Intel CorporationInventors: Bruce Querbach, Pete D. Vogt
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Patent number: 10216657Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.Type: GrantFiled: September 30, 2016Date of Patent: February 26, 2019Assignee: INTEL CORPORATIONInventors: Bruce Querbach, Pete D. Vogt
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Patent number: 10146711Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.Type: GrantFiled: June 28, 2016Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Bill Nale, Kuljit S. Bains, George Vergis, Christopher E. Cox, James A. McCall, Chong J. Zhao, Suneeta Sah, Pete D. Vogt, John R. Goles
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Patent number: 10120749Abstract: ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O connectors instead of arbitrarily routed. As such, the data paths of the memory subarrays can be exclusively routed to a specific I/O connector. The I/O connector can be uniquely associated with a single memory subarray, or multiple memory subarrays can be mapped to a specific I/O connector. The mapping is in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated one or multiple memory subarrays.Type: GrantFiled: September 30, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventor: Pete D. Vogt
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Publication number: 20180210674Abstract: Methods and apparatus to provide heterogeneous memory die stacking for energy efficient computing are described. In one embodiment, a Phase Change Memory with Switch (PCMS) die is coupled to a Dynamic Random Access Memory (DRAM) die and a Central Processing Unit (CPU) die. CPU checkpointing state data is stored in the PCMS die first before transferring the checkpointing data to a backup media at a later and more extended time. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 9, 2017Publication date: July 26, 2018Applicant: Intel CorporationInventor: Pete D. Vogt
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Patent number: 10031802Abstract: Apparatus, systems, and methods to embed ECC data with cacheline data in a memory page are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive a request to read or write data to a memory device, wherein the data is mapped to a memory page comprising a plurality of cache lines, displace at least a portion of the plurality of cache lines to embed error correction code information with the data, and remap the portion of the plurality of cache lines to another memory location, and retrieve or store the data and the error correction code information on the memory page. Other embodiments are also disclosed and claimed.Type: GrantFiled: June 28, 2013Date of Patent: July 24, 2018Assignee: Intel CorporationInventor: Pete D. Vogt
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Publication number: 20180130505Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board that includes a first row of elements including a first CPU positioned between first and second groups of dual in-line memory modules (DIMMs). The printed circuit board also includes a second row of elements including a second CPU positioned between third and fourth groups of DIMMs. The apparatus also includes a third row of elements including a fifth group of DIMMs, wherein the second row of elements is positioned between the first row of elements and the third row of elements. Other embodiments are described and claimed.Type: ApplicationFiled: November 9, 2017Publication date: May 10, 2018Inventors: Bruce QUERBACH, Pete D. VOGT
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Publication number: 20180122779Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.Type: ApplicationFiled: September 8, 2017Publication date: May 3, 2018Inventors: Pete D. VOGT, Andre SCHAEFER, Warren MORROW, John B. HALBERT, Jin KIM, Kenneth D. SHOEMAKER
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Publication number: 20180095821Abstract: ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O) connectors to interface with an external device such as a controller. The memory device includes multiple arrays or subarrays that are specifically mapped to I/O connectors instead of arbitrarily routed. As such, the data paths of the memory subarrays can be exclusively routed to a specific I/O connector. The I/O connector can be uniquely associated with a single memory subarray, or multiple memory subarrays can be mapped to a specific I/O connector. The mapping is in accordance with an error checking and correcting (ECC) code matrix, where a code of the ECC code matrix corresponding to the specific I/O connector is to check and correct data corruption errors and I/O errors for the associated one or multiple memory subarrays.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventor: Pete D. VOGT
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Publication number: 20180095909Abstract: Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed circuit board (PCB) that includes a printed circuit board defining a length and a width, the length being greater than the width. The apparatus includes a first row of elements on the PCB, including a first memory region configured to receive at least one memory module. The apparatus includes a second row of elements on the PCB, including a first central processing unit (CPU) socket configured to receive a first CPU, and a second CPU socket configured to receive a second CPU, the first CPU socket and the second CPU socket positioned side by side along the width of the PCB. The apparatus also includes a third row of elements on the PCB, including a second memory region configured to receive a at least one memory module, wherein the second row of elements is positioned between the first row of elements and the third rows of elements.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Bruce QUERBACH, Pete D. VOGT