Abstract: Apparatus for generating and displaying data on a monitor 28 such as a CRT of LCD display. The display is comprised of a plurality of images, each located at positions on the face of the monitor defined by multi-digit coordinate values in a multi-coordinate system. Units of data are stored in linear display memory 26, each such unit of data corresponding to and defining the image to be displayed at one of said positions. The apparatus includes a circuit 60 which places selected bits of said multi-digit coordinate values in a preselected order to define the address or offset in said linear display memory at which is located the corresponding unit of data.

Abstract: A keyboard controller is used to drive the PDEN pins on DIMMs. A PC has a keyboard controller with a plurality of programmable input/output (I/O) pins. The state of the programmable I/O pins can be set by software. The pins are coupled to individual PDEN pins on the DIMMs. When the programmable I/O pins are activated, the PDEN pins are driven active and each DIMM outputs a signal indicating its characteristics. The signals are latched and stored for use by a memory controller.

Abstract: An SDRAM memory controller that provides both burst four and single data transfers while keeping the SDRAM in burst four mode. A memory controller uses a DQMB?7:0! signal and a precharge command to stop the transference of data on the data bus during the time that the last 3 data elements would have been transferred. Specifically, during a single read, DQMB?7:0! is set high for two clock cycles causing the data bus to float during the time that the second and third data elements would have been on the bus. During a single write, DQMB?7:0! is set high for two clock cycles thereby preventing the second and third data elements from being written to memory. During a read, the precharge command causes the bus to float during the time the fourth element would have been on the bus. During a write, the precharge command prevents the fourth data element from being written.

Abstract: A computer system having a unified memory architecture (UMA) with a central SDRAM memory can be accessed by multiple devices. Arbitration logic receives and arbitrates among the memory requests. The memory controller indicates when the arbitration logic may issue a grant. The memory controller has two arbitration points during a memory cycle, an early one and a late one. A central processing unit (CPU), or other device, that misses the early arbitration point can still get memory access during the memory cycle by submitting a memory request before the late arbitration point.

Abstract: A memory bandwidth allocation scheme in a computer system having a unified memory architecture. When a first device requesting access to a resource detects that two higher priority devices are also requesting access to the same resource, the first device shuts itself down. Accordingly, the first device deactivates its access request signals and clears its buffers. Then, the first device reactivates itself when it receives a graphics VSYNC signal. This allocation scheme ensures that the arbiter will not get stuck in a loop serving only high priority requests and not serving lower priority requests.

Abstract: An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.