Abstract: A method and system for enabling personalization of services for a user. A first and second computerized service system that includes a first and second server, respectively, is utilized. An information server of a computerized information system receives a different request from the first and second server for first and second personalization information of the user, respectively. The first and second personalization information enables a first and second entity that uses the first and second server to provide a service to the user in response to the user having previously requested the service from first and second entity, respectively. The information server determines that first and second criteria for the first and second entity to receive the first and second personalization information, respectively, have been satisfied, after which the information server sends the first and second personalization information to the first and second server, respectively.

Abstract: A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command.

Abstract: A stream prefetch engine performs data retrieval in a parallel computing system. The engine receives a load request from at least one processor. The engine evaluates whether a first memory address requested in the load request is present and valid in a table. The engine checks whether there exists valid data corresponding to the first memory address in an array if the first memory address is present and valid in the table. The engine increments a prefetching depth of a first stream that the first memory address belongs to and fetching a cache line associated with the first memory address from the at least one cache memory device if there is not yet valid data corresponding to the first memory address in the array. The engine determines whether prefetching of additional data is needed for the first stream within its prefetching depth. The engine prefetches the additional data if the prefetching is needed.

Abstract: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.

Abstract: A list prefetch engine improves a performance of a parallel computing system. The list prefetch engine receives a current cache miss address. The list prefetch engine evaluates whether the current cache miss address is valid. If the current cache miss address is valid, the list prefetch engine compares the current cache miss address and a list address. A list address represents an address in a list. A list describes an arbitrary sequence of prior cache miss addresses. The prefetch engine prefetches data according to the list, if there is a match between the current cache miss address and the list address.

Abstract: Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Abstract: Integrated circuits contain core logic that is powered using a power supply signal. The core logic contains simultaneously switching circuitry. The simultaneously switching circuitry contributes to noise on the power supply signal. Balancing circuitry may be provided on the integrated circuit to compensate for the simultaneously switching circuitry in the core logic. The balancing circuitry may receive an input signal that is out of phase with respect to the input to the core logic. As the balancing circuitry switches out of phase with the simultaneously switching circuitry of the core logic, the noise contribution from the core logic is compensated and power supply noise on the power supply signal is minimized.

Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Abstract: Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

Abstract: Computer-aided design tools analyze a custom logic design for a programmable logic device integrated circuit. The tools identify distinct clock domains in the design. The tools also identify which of the clock domains are synchronous. The tools examine the synchronous clock domains to determine which of the clock domains have required fixed phase relationships. Clocks for clock domains that do not have required fixed relationships can be adjusted in phase to minimize power supply simultaneous switching noise. Noise may be minimized by making clock phase adjustments using a programmable phase-locked loop circuit.

Abstract: Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to produce configuration data containing alternative configuration memory settings each of which is optimized for programmable logic devices with different performance characteristics. During manufacturing, programmable logic devices are tested to identify their performance characteristics. A bin code is stored in non-volatile memory in each device to specify which performance characteristics are associated with that device. During programming, the bin code of a given device is used to decide which of the alternative configuration memory settings are to be discarded. The retained subset of the configuration data is loaded into configuration memory in the given device.

Abstract: A method for determining a current spectrum for a circuit design is provided. The method includes determining timing characteristics and power consumption characteristics for the circuit design. From the timing characteristics and the power consumption characteristics a time domain current waveform is constructed. The time domain current waveform is then converted to a frequency domain current waveform. With the frequency domain waveform, one skilled in the art can then identify a location and an amount of decoupling capacitors for a printed circuit board housing the circuit design based on the frequency domain current waveform. A computing system configured to perform the method is also provided.

Abstract: A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.

Abstract: An expert system is used to recommend a customized solution for a customer. The expert system includes a set of scenarios each of which includes default facts and is associated with a detailed rule base that when applied in isolation to the default facts fully determines a prototype solution. A particular scenario is selected from the set based at least on user input. A customized solution is generated by applying the detailed rule base associated with the particular scenario to facts based at least on the user input and any default facts of the particular scenario that complement and do not conflict with the facts that are based at least on the user input. The customized solution is iteratively refined.

Abstract: A number of apparatii for condensing water from the atmosphere are described, whereby atmospheric air is drawn through an enclosed space and moisture condenses on plates or similar contained within the enclosed space and subsequently collected. Most of the apparatii include means to increase the flow of air through the enclosed space to increase the efficiency of moisture collection. A typical apparatus includes a body (11) supporting condenser plates (15) of conical or frusto-conical configuration. Extractor fans, the operation of which are controlled by humidity sensing switches and temperature sensors, provide the increased flow. To promote condensation, typically, cooling ducts (49) are provided through which air-conditioned cool air is passed.

Abstract: A device is described for providing an emergency exit from burning buildings, for installation and/or removal of bulky items from the upper levels of buildings, or for rapid deployment of military and other personnel from helicopters. The device (1) comprises a helical tubular body member (2) comprising three coils of copper tube. The outer ends of the body member (2) are configured such that they form an upper outlet end (3) and a lower outlet end (4) disposed substantially in the same vertical plane. At each upper outlet end (3) and lower outlet end (4) is affixed a respective chuck (5a,b), each chuck (5a, b) comprising an outer internally threaded body (6a, b) which can reversibly operate respective multiple jaws (7) to bear upon a rope (8) which passes through the upper chuck (5a), the coils of the body member (2) and the lower chuck (5b). If the device is to be arrested in use, a locking clamp (15) can be positioned within reach of the user.

Abstract: A wire holder (10) to attach wire (22) to metal posts known as star pickets (23) which comprise three equi-spaced flanges (24) at least one of which being provided with a plurality of spaced apertures (25). The holder (10) includes a capturing part (12) and an attaching part (19) which may be separate or integral. The capturing part (12) is located about the picket (23) to capture the wire (22) and terminates in first and second ends (13, 14), adapted to be located on opposite sides of the flange (24) adjacent the aperture (25); and the attaching part (19) cooperates with the capturing part (12) to secure the holder (10) to the picket (23). The first and second ends (13, 14) can be of various configurations, including two looped portions through which a U-shaped attaching part (19) may pass through, or a single loop at one end with a pin-like member at the other end.

Abstract: Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

Abstract: A circuit (FIG. 1) for generating a current impulse comprises an avalanche transistor 2 which responds to a stimulus to apply an electrical impulse to the bases of a plurality of further avalanche transistors 3, 6. The further transistors respond to the impulse to discharge respective equal capacitors 9-12 through a laser diode 7. Further equal capacitors 22-25 connect the emitters of the transistors to the common junction of the transistor 2 and an impedance 21 to generate the electrical impulse when the transistor 2 responds to the stimulus. The arrangement of the further capacitors ensures that once one further transistor begins to conduct, the electrical stress on the others is increased, thus ensuring the further transistors simultaneously avalanche.