Patents by Inventor Peter A. Child

Peter A. Child has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9424858
    Abstract: A system and method and system for receiving communications signals coded at transmission in a frequency hopping waveform includes a sensor that receives acoustic data. A detector joined to the sensor receives the data and separates signals from background noise. Logic determines when the signal ends. Clusters of signals are processed and grouped into combinations of symbols. A computer translates these symbols into messages using a codebook. When multiple possibilities exist, the message is selected from the codebook that maximizes a similarity score. Additional logic is provided to handle situations where unwanted signals are mixed into an otherwise valid symbol sequence, to find the best subset of signals forming a valid message. Selected messages are provided as output to users. In further details, the detector filters the acoustic data and transforms it to the frequency domain. A power spectrum is calculated for detecting signals in specific frequency bands.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: August 23, 2016
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David J Pistacchio, Peter A Child
  • Patent number: 8768647
    Abstract: A high performance solid-state heading sensor for underwater towed arrays is taught that combines high quality MEMS sensor components with data processing filters to resolve performance limitations present in prior art heading sensors. The heading sensor employs rate gyroscopes, accelerometers, magnetometers and a customized Kalman filter formulation implemented on a micro-controller to improve performance in determining the roll, pitch and heading of a towed array.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 1, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Ahmed S. Zaki, Timothy B. Straw, Michael J. Obara, Peter A. Child
  • Patent number: 4833097
    Abstract: A process for the fabrication of shallow p.sup.+ and n.sup.+ doped layers suitable for the sources and drains of submicron CMOS transistors comprises applying a layer of polysilicon (1) over a gate oxide layer (2) which is surrounded by a field oxide isolation layer (3) located on a suitable substrate (4) and applying a resist layer (5) to the polysilicon layer in a selected region of the polysilicon layer overlying the gate oxide to define a gate electrode. Selective ion implantation then takes place to form the source and drain regions (6, 7), the implementation extending through the oxide layer to a limited extent except in the region masked by the resist layer. The polysilicon layer and resist layer are then etched away to leave a gate electrode (8) extending from the oxide layer (2) and the source and drain regions are then activated and difussed to .about.0.1 .mu.m junction depth.
    Type: Grant
    Filed: April 4, 1988
    Date of Patent: May 23, 1989
    Inventors: Alan L. Butler, Peter A. Childs