Patents by Inventor Peter A Keevill

Peter A Keevill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing
    Patent number: 6687315
    Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: February 3, 2004
    Assignee: Discovision Associate
    Inventors: Peter A Keevill, Dawood Alam, John M. Nolan, Matthew J Collins, Thomas Foxcroft, David H. Davies, Jonathan Parker
  • Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing
    Publication number: 20030142764
    Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.
    Type: Application
    Filed: November 27, 2001
    Publication date: July 31, 2003
    Inventors: Peter A Keevill, Dawood Alam, John M Nolan, Matthew J Collins, Thomas Foxcroft, David H Davies, Jonathan Parker
  • Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing
    Patent number: 6359938
    Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: March 19, 2002
    Assignee: Discovision Associates
    Inventors: Peter A Keevill, Dawood Alam, John M. Nolan, Matthew Collins, Thomas Foxcroft, David H. Davies, Jonathan Parker