Abstract: Various embodiments disclose a method including detecting, by a first node in a mesh network while the first node is operating in a normal power mode, an outage event; in response to detecting the outage event, switching to operating the first node and a first memory of the first node in a low power mode, wherein the first memory is capable of switching between operating in the normal power mode and in the low power mode where an amount of power used by the first memory is reduced; and while operating the first node and the first memory in the low power mode: generating, by the first node, a first message; securing, by the first node using a key retrieved from the first memory, the first message; and sending, by the first node, the first message to a second node in the mesh network.

Abstract: The present disclosure generally pertains to cyber-attack resiliency assessment systems and methods. In some embodiments, the system may be configured to assess susceptibility of an operational system and its components to specific cyber-attacks and predict an impact of such attacks and impact to a mission which the operational system is intended to perform and complete.

Abstract: Various embodiments disclose a computer-implemented method for sending a message associated with an outage event, comprising, at a first node in a network, receiving a key from a second node in the network, wherein the second node is adjacent to the first node; storing the key in a first memory, wherein the first memory is capable of operating in a low power mode; detecting an outage event; in response to detecting the outage event, operating a first processor in the low power mode; and via the first processor operating in the low power mode: generating a message, securing the message using the key, and sending the message to the second node.

Abstract: Techniques for messaging based on trust levels and resource limitations in a mesh network include receiving, by a first node of a mesh network, a message; determining, by the first node, a security key type based on a resource parameter associated with a neighbor node included in the mesh network; securing, by the first node, the message using a security key of the security key type; and transmitting, by the first node, the secured message to the neighbor node. The resource parameter associated with the neighbor node comprises at least one of an amount of memory used to decrypt the secured message at the neighbor node, an amount of power used to decrypt the secured message at the neighbor node, or an indication of an amount of power remaining at the neighbor node.

Abstract: A computer-implemented method of transmitting messages within a mesh network comprises: receiving at a first node included within the mesh network a network message that is to be broadcast within the mesh network; determining a security key type based on at least one of a resource parameter associated with at least one neighbor node included in the mesh network or an attribute of the network message; securing the network message with a security key of the security key type to generate n secured network message; and broadcasting the secured network message to one or more other nodes included in the mesh network that are directly connected to the first node.

Abstract: Various embodiments set forth a method comprising receiving, at a server node from a client node, a client compression dictionary that includes one or more first mappings between one or more first index values and one or more data entries included in a certificate cache of the client node; identifying, in response to receiving the client compression dictionary and based on the client compression dictionary, one or more certificates that should be transmitted to the client node; and transmitting, from the server node to the client node, the one or more identified certificates.

Abstract: A computer-implemented method of transmitting messages within a mesh network comprises: receiving at a first node included within the mesh network a network message that is to be broadcast within the mesh network; determining a security key type based on at least one of a resource parameter associated with at least one neighbor node included in the mesh network or an attribute of the network message; securing the network message with a security key of the security key type to generate n secured network message; and broadcasting the secured network message to one or more other nodes included in the mesh network that are directly connected to the first node.

Abstract: Various embodiments disclose a computer-implemented method for sending a message associated with an outage event, comprising, at a first node in a network, receiving a key from a second node in the network, wherein the second node is adjacent to the first node; storing the key in a first memory, wherein the first memory is capable of operating in a low power mode; detecting an outage event; in response to detecting the outage event, operating a first processor in the low power mode; and via the first processor operating in the low power mode: generating a message, securing the message using the key, and sending the message to the second node.

Abstract: A removable module for a phased array, the module including: a circuit board having a ground plane formed on one side of the circuit board; an antenna mounted on and extending away from a topside of the circuit board; circuitry on a backside of the circuit board, the circuitry including an RF front end circuit coupled to the antenna; and a group of one or more first connecters mounted on the backside of the circuit board, the first connectors for physically and electrically connecting and disconnecting the module from a master board through a corresponding group of one or more matching second connectors on the master board, the first connectors on the module having electrically conductive lines for carrying an externally supplied LO signal for the RF front end circuit and an IF signal for or from the RF front end circuit.

Abstract: A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.

Abstract: A removable module for a phased array, the module including: a circuit board having a ground plane formed on one side of the circuit board; an antenna mounted on and extending away from a topside of the circuit board; circuitry on a backside of the circuit board, the circuitry including an RF front end circuit coupled to the antenna; and a group of one or more first connecters mounted on the backside of the circuit board, the first connectors for physically and electrically connecting and disconnecting the module from a master board through a corresponding group of one or more matching second connectors on the master board, the first connectors on the module having electrically conductive lines for carrying an externally supplied LO signal for the RF front end circuit and an IF signal for or from the RF front end circuit.

Abstract: A voltage-switched class-S amplifier circuit includes an output stage configured to receive at least one control signal and operative to generate an output signal as a function of the at least one control signal. The amplifier circuit further includes a driver circuit coupled with the output stage. The driver circuit is configured to receive an input bit stream signal and is operative to generate the control signal as a function of the input bit stream signal in such a manner that a common mode component is eliminated from the control signal.

Abstract: A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.

Abstract: A bitstream generator includes at least first and second bitstream generator stages connected in a cascaded arrangement. The first bitstream generator stage includes a first adder which receives an input signal and generates a first error signal indicative of a difference between the input signal and a first bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the first bitstream generator stage. The second bitstream generator stage includes a second adder which receives the first error signal and generates a second error signal indicative of a difference between the first error signal and a second bitstream candidate representing a closest approximation to the input signal among multiple bitstream candidates generated by the second bitstream generator stage. A third adder in the bitstream generator receives the first and second bitstream candidates and generates an output signal more closely approximating the input signal.

Abstract: An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.

Abstract: A composite amplifier providing digitally selectable amplification includes a plurality of channels and a combiner. Each of the channels includes a digitally controllable selector, a Class-S power amplifier, and bandpass filter. The digitally controllable selector selectively couples a digital bitstream to the amplifier. The amplifier receives the digital bitstream and provides an amplified signal. The bandpass filter generates a filtered signal as a function of the amplified signal. The combiner couples filtered signals provided by the channels to form a composite output signal.

Abstract: An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.

Abstract: A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

Abstract: A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

Abstract: A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can be combined again to reconstruct the original function. The method in accordance with the present disclosure limits the amount of input power necessary to achieve higher output power, lowers operating voltage and improves power amplifier efficiency.