Patents by Inventor Peter A. Laubenstein

Peter A. Laubenstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONFIGURABLE FAULT AND CONTROL SAFETY ARCHITECTURE FOR INVERTER SYSTEM
    Publication number: 20230198377
    Abstract: A system for a direct-current (DC) to alternating current (AC) inverter includes: a memory configured to store instructions; a main microcontroller configured to execute the stored instructions to control the inverter during non-timing-critical operation; and a safety controller configured to control the inverter during timing-critical operation.
    Type: Application
    Filed: December 17, 2021
    Publication date: June 22, 2023
    Applicant: Delphi Technologies IP Limited
    Inventors: Lokesh GONA, Clinton W. ERICKSON, Mitchell S. COHEN, John Mark DIKEMAN, Peter A. LAUBENSTEIN, Mark W. GOSE
  • Electrical load controller with fault detection
    Patent number: 9800042
    Abstract: A controller configured to detect fault conditions in a circuit that operates an electrical-load includes a gate-driver and a voltage-detector. The gate-driver is configured to control a gate-current to a switching-device. The gate-current is controlled such that the switching-device is operated in a linear-state when the switching-device transitions from an on-state to an off-state. The voltage-detector is configured to determine a voltage-drop across the switching-device. The controller is configured to indicate a no-fault condition when the voltage-drop is greater than a voltage-threshold for more time than a no-fault interval after the switching device is operated from the on-state to the linear-state.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: October 24, 2017
    Assignee: DELPHI TECHNOLOGIES, INC.
    Inventors: Marc R. Engelhardt, Kevin M. Gertiser, Vijayakumaran Nair Balakrishnan Nair, Peter A. Laubenstein
  • ELECTRICAL LOAD CONTROLLER WITH FAULT DETECTION
    Publication number: 20160238652
    Abstract: A controller configured to detect fault conditions in a circuit that operates an electrical-load includes a gate-driver and a voltage-detector. The gate-driver is configured to control a gate-current to a switching-device. The gate-current is controlled such that the switching-device is operated in a linear-state when the switching-device transitions from an on-state to an off-state. The voltage-detector is configured to determine a voltage-drop across the switching-device. The controller is configured to indicate a no-fault condition when the voltage-drop is greater than a voltage-threshold for more time than a no-fault interval after the switching device is operated from the on-state to the linear-state.
    Type: Application
    Filed: February 16, 2015
    Publication date: August 18, 2016
    Inventors: MARC R. ENGELHARDT, KEVIN M. GERTISER, VIJAYAKUMARAN NAIR BALAKRISHNAN NAIR, PETER A. LAUBENSTEIN
  • Current and temperature sensing of standard field-effect transistors
    Patent number: 8489357
    Abstract: An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 16, 2013
    Assignee: Delphi Technologies, Inc.
    Inventors: Jack L. Glenn, Mark A. Gose, Peter A. Laubenstein, Seyed R. Zarabadi
  • CURRENT AND TEMPERATURE SENSING OF STANDARD FIELD-EFFECT TRANSISTORS
    Publication number: 20110112792
    Abstract: An apparatus and method of determining the junction temperature (Tj) and drain-source current (Ids) of a standard FET within a multi-FET module includes a control IC managing one or more 3 terminal standard FETs within the same package, calculating Tj and Tds for one or more FETs in one or more packages, and protecting each FET against short circuit faults while allowing high current transients, such as inrush currents from a lamp load.
    Type: Application
    Filed: July 23, 2009
    Publication date: May 12, 2011
    Applicant: DELPHI TECHNOLOGIES, INC.
    Inventors: Jack L. Glenn, Mark A. Gose, Peter A. Laubenstein, Seyed R. Zarabadi