Abstract: A silicon-based image sensor has an upconversion layer of crystals. The silicon-based image sensor receives light from a common beam splitter with a second image sensor. An optical band pass filter cooperates with the common beam splitter to pass some of the light to be incident on the upconversion layer of crystals in a second range of wavelengths, which will be absorbed and converted by the upconversion layer of crystals into a third range of wavelengths, and then the third range of wavelengths is transmitted onto the pixels in the silicon-based image sensor. A pulse repetition frequency decoder cooperates with the upconversion layer of crystals to decode a pulse repetition frequency of a laser flash in the second range of wavelengths passed by the optical band pass filter and subsequently upconverted by the upconversion layer of crystals and then captured by the pixels of the silicon-based image sensor.

Abstract: A silicon-based image sensor can have i) a pixel array with one or more pixels and ii) an upconversion layer of crystals on at least one of a front side and a backside of the silicon-based image sensor. A pulse repetition frequency decoder cooperates with the upconversion layer of crystals to decode a pulse repetition frequency of a laser flash captured by one or more of the pixels of the silicon-based image sensor. The pulse repetition frequency decoder can use a known frame rate of the silicon-based image sensor and a decay time of an upconverting emission from the upconversion layer of crystals to decode the pulse repetition frequency of the laser flash.

Abstract: In one embodiment, an imager has an array of photodetectors, each of which accumulates charge during an integration period as a result of light detected during the integration period, the array having a charge capacity which increases during the integration period. A charge capacity controller coupled to the imager adjusts how the imager increases the charge capacity of the array based upon the brightness distribution detected by the imager during at least one previous integration period.

Abstract: An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients and an amorphans silicon a corbide layer.

Abstract: An extended dynamic range imager. An array of pixels provides an output signal for each pixel related to an amount of light captured for each pixel during an integration period. A row of extended dynamic range (XDR) sample and hold circuits having an XDR sample and hold circuit for each column of the array captures an XDR signal related to a difference between the output signal and an XDR clamp level to which the pixel is reset at a predetermined time before the end of the integration period. A row of linear sample and hold circuits having a linear sample and hold circuit for each column of the array captures a linear signal related to a difference between the output signal and an initial output signal to which the pixel is reset at the beginning of the integration period.

Abstract: An infrared imager includes an array of capacitance sensors that operate at room temperature. Each infrared capacitance sensor includes a deflectable first plate which expands due to absorbed thermal radiation relative to a non-deflectable second plate. In one embodiment each infrared capacitance sensor is composed of a bi-material strip which changes the position of one plate of a sensing capacitor in response to temperature changes due to absorbed incident thermal radiation. The bi-material strip is composed of two materials with a large difference in thermal expansion coefficients.

Abstract: A imager has an array of photodetectors, each of which accumulates charge during an integration period as a result of light detected during said integration period, said array having a charge capacity which increases during the integration period. A charge capacity controller coupled to said imager adjusts how the imager increases the charge capacity of the array based upon the brightness distribution detected by said imager during at least one previous integration period.

Abstract: A defect corrector for a solid-state imager having a number of defective pixels less than the total number of pixels in the imager in which only defect correction signals associated with the defective pixels are generated. The defect correction signals are then combined with photoresponse signals from the corresponding defective pixels, so as to provide a defect compensated photoresponse signal for each of the defective pixels.

Abstract: A defect corrector for a solid-state imager in which temperature tracking defect correction signals associated with the defective pixels are generated. The temperature tracking defect correction signals are combined with photoresponse signals from the corresponding defective pixels to provide defect compensation for the photoresponse signal developed from each of the defective pixels.

Abstract: A color television camera including a selectively removable infrared (IR) rejection filter and controllable weighting luminance signal matrixing circuitry features increased low-light sensitity. During low-light conditions, the infrared rejection filter is removed from the optical path of the camera, permitting infrared light to pass to the camera's imaging means; the weighting of the controllable weighting luminance signal matrixing circuitry is altered to provide a more accurate visual representation; and the color subcarrier signal is disabled so that the camera produces only a black-and-white signal.

Abstract: First and second output signals are taken from a floating element in a CCD charge transfer channel and from the terminal drain diffusion of that CCD charge transfer channel. The floating element is part of an electrometer, and the electrometer response is wide-band sampled at the CCD charge transfer channel clocking rate. Current flow through the terminal drain diffusion is sensed by the input circuit of a low l/f noise transresistance amplifier. Continuous-frequency-spectrum low-noise output signal is generated from the low-frequency components of the transresistance amplifier response and from the high-frequency components of the processed second output signal. Subsequent filtering removes unwanted clock and aliased frequency components.

Abstract: A television camera includes optics for directing light from an illuminated scene to an imager, a signal processor for developing a video signal from an imager supplied signal, and apparatus for controlling the magnitude of the developed video signal to reduce brightness variations (flicker) caused by artificial scene illumination. The controlling apparatus develops a first signal representative of the average illumination of the scene, a second signal representative of the amount of the directed light which the imager actually responds to, and a control signal in response to the signal processor for controlling the magnitude of the developed video signal.

Abstract: A CCD delay line may be tapped using a floating-diffusion electrometer at the tap. Charge sensing is made non-destructive by not resetting the floating diffusion to a reset drain after charge sensing. The resulting charge integration on the floating diffusion causes a smearing of the samples described by successive charge packets. The smearing is in the baseband frequencies of the sample frequency spectrum, but does not appreciably affect the subspectra surrounding harmonics of the delay line clock rate. Consequently, smear-free response to the floating-gate electrometer output signals can be obtained by synchronously detecting them at a harmonic of the delay line clock rate. Using floating-diffusion electrometers, rather than floating-gate electrometers, to sense charge packet amplitudes at taps along a CCD delay line lowers the noise in the output response of output-weighted, charge-coupled-devive transversal fiters.

Abstract: The parallelly arranged charge transfer channels in the image register of a field transfer type CCD imager are clocked with a number of phases equal to 2m, m being a positive integer equal to two or more, during image transfer. The successive gate electrodes receiving each cycle of successive-in-time clock phases during image transfer are considered to be consecutively ordinally numbered first through 2m.sup.th. During the image integration times of odd fields, the first gate electrode in each cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each first gate electrode. During the integration times of even fields, the (m+1).sup.th gate electrode in each gate-electrode cycle of the image register is biased to induce a potential energy barrier thereunder, and photoresponse charge is collected under the gate electrodes of the image register exclusive of each (m+1).sup.

Abstract: Alignment of a plurality of thinned substrate solid-state imagers mounted at the outputs of an optical assembly is accomplished optically, without the necessity to electrically operate the imagers. Light blocking alignment indicia, such as a chevron pattern, are deposited over the electrode structure of the chip. When the imagers are positioned at the optical assembly outputs and light is used to illuminate the imagers electrode structure side, the alignment indicia are visible at the optical assembly input and can be used for alignment of the imagers.

Abstract: Charge transfer device output signals typically include an information component which is contaminated with both on-chip amplifier noise and reset noise. For reducing these noise components, the device output signal is applied to first and second synchronous detectors. The first synchronous detector is responsive to a first reference carrier signal for maximizing at its output the information component while the second synchronous detector is responsive to a second reference carrier for maximizing at its output the noise components. The synchronous detector output signals are then differentially combined so as to substantially reduce the noise components from the contaminated information component.

Abstract: Stripe patterns of varying spatial frequency, formed in the top-metalization of a back-illuminated solid-state imager, facilitate on-line measurement of contrast transfer function during wafer-probe testing. The imager may be packaged to allow front-illumination during in-the-field testing after its manufacture.

Abstract: Conventionally, solid-state imager chips are packaged in ceramic IC packages. In accordance with the invention, unpackaged imager chips are bonded to a light transmissive carrier having an area substantially larger than the area of the imager chip. The light transmissive carrier both firmly supports the imager chip and includes a metallization pattern which contacts the imager chip and provides for its electrical connections to external drive and signal processing circuitry. In a preferred embodiment, the photosensitive side of a thinned-substrate solid-state imager chip is directly bonded to the exit port of a prism. The prism exit port has the metallization pattern formed thereon and includes edge connectors at its periphery for connecting to the external circuitry.

Abstract: The output signal from the CCD output register of a semiconductor imager having a floating-gate or floating-diffusion type of output stage is applied to a differentiation circuit. The response of the differentiator circuit to the introduction of charge under the floating element is synchronously detected at output register clock rate to obtain video samples with low reset noise. This is a single sampling process, which avoids the double sampling required in correlated double sampling to reduce reset noise, and which can provide for horizontal peaking.