Abstract: An exercise machine is disclosed. The exercise machine comprises a tension generating device. The exercise machine comprises a translatable arm mount coupled to the tension generating device. The exercise machine comprises an arm coupled to the translatable arm mount. The exercise machine comprises a cable coupled to the tension generating device via the arm.

Abstract: An exercise machine is disclosed. The exercise machine comprises a tension generating device. The exercise machine comprises a translatable arm mount coupled to the tension generating device. The exercise machine comprises an arm coupled to the translatable arm mount. The exercise machine comprises a cable coupled to the tension generating device via the arm.

Abstract: An exercise device includes a resistance unit having a connecting gear. It further includes a cable. It further includes an arm that routes the cable to an actuator. The arm is rotatable relative to the resistance unit about the connecting gear, the arm having a central axis. The arm includes a control that mechanically disengages a locking mechanism from the connecting gear. The control is activated by an activation force substantially directed either toward the central axis of the arm, along a length of the arm, or about the central axis. The activation force is mechanically converted into linear force along the arm that disengages the locking mechanism from the connecting gear.

Abstract: An exercise machine is disclosed. The exercise machine comprises a tension generating device. The exercise machine comprises a translatable arm mount coupled to the tension generating device. The exercise machine comprises an arm coupled to the translatable arm mount. The exercise machine comprises a cable coupled to the tension generating device via the arm.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.

Abstract: A multi-step plasma etch method for etching a tapered via having uniform bottom diameter ("CD") and extending through the resist and into the oxide layer of a coated semiconductor substrate, and a coated semiconductor substrate whose coating has been plasma etched to define such a tapered via. The first step of the inventive method is an anisotropic oxide plasma etch operation, preferably employing a plasma consisting primarily of CF.sub.4, which produces a non-tapered via having diameter substantially equal to CD and extending through the resist and into the oxide layer. A preferred embodiment of the inventive method includes a second step defining an upper sloping via portion without significantly increasing the diameter of a lower portion of the non-tapered via. This second step is a tapered resist plasma etch operation employing a mixture of oxygen (O.sub.2) and CF.sub.4. The slope of the upper sloping via portion may be controlled by varying the ratio of oxygen to CF.sub.4.