Patents by Inventor Peter A. Morrison

Peter A. Morrison has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6478750
    Abstract: A hair collection device useful in testing for drugs and hazardous materials, comprising an outer barrel with a barrel lumen and a hair collection oriface; an inner hair storage container insertable in and removable from the barrel lumen, and comprising a hair storage lumen and a second hair collection oriface; and a hair snare insertable into the hair storage lumen and extendable through both of the hair collection orifaces.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: November 12, 2002
    Inventors: Janet F. Morrison, Peter A. Morrison, Carl M. Selavka, Thomas M. Eden, Chip B. Thuss, Kenneth C. Hopper, John S. Sundsmo
  • Patent number: 5155735
    Abstract: Apparatus and methods for performing parity checking in an environment in which devices which perform parity checking and those which do not are connected to the same synchronous bus. The bus includes a parity enable line, which carries a parity enable signal indicating that the device transmitting data on the bus is a parity device which provides the parity of the data it transmits, a parity line, which carries the parity of the data being transmitted, and a parity error line which carries a parity error signal indicating whether the receiving device detected a parity error. The data is transmitted in a first bus cycle, the parity enable signal and the parity are transmitted in the following bus cycle, and the receiving device transmits the parity error signal in the next bus cycle after that.
    Type: Grant
    Filed: March 31, 1988
    Date of Patent: October 13, 1992
    Assignee: Wang Laboratories, Inc.
    Inventors: Robert C. Nash, Peter A. Morrison
  • Patent number: 5101478
    Abstract: An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components.
    Type: Grant
    Filed: August 4, 1988
    Date of Patent: March 31, 1992
    Assignee: Wang Laboratories, Inc.
    Inventors: Andrew N. Fu, Tom R. Kibler, James B. MacDonald, Robert C. Nash, Stephen W. Olson, Bhikoo J. Patel, Robert R. Trottier, Kevin T. Mahoney, David L. Whipple, Peter A. Morrison
  • Patent number: 5010823
    Abstract: This invention relates to an elongated flexible housing containing coexteve explosive and propellant charges. The housing is adapted to be attached to a structure to be severed and the parts separated. The explosive charge is a shaped-charged for first severing the structure into two parts. The propellant charge separates the severed parts one from another.
    Type: Grant
    Filed: July 13, 1990
    Date of Patent: April 30, 1991
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Peter A. Morrison
  • Patent number: 4539682
    Abstract: Method and apparatus permitting a multi-module digital system, such as a puter, having built-in test hardware associated with each module, including a plurality of signal processing units to communicate over two wire circuitry not only the existence of a failure of a particular module, but also its causality. This is accomplished by means of a four state signaling circuit interposed between each signal processing unit of a particular module and a module built-in test circuit which operates once an error output is reported by a signal processing unit to provide a further four state indication of the details of the failure.
    Type: Grant
    Filed: April 11, 1983
    Date of Patent: September 3, 1985
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Jan S. Herman, Peter A. Morrison, Gerald P. Richards