Patents by Inventor Peter A. Percosan

Peter A. Percosan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processor with an integer multiplication function on a fractional multiplier
    Patent number: 5363322
    Abstract: A data processing system (10) which primarily supports fractional multiplication operations has a multiplication logic circuit (20) for executing integer multiplication functions efficiently. During an integer multiplication function, two multiplicands are multiplied together as if the multiplication function was fractional. A predetermined accumulation input is stored and shifted to the right by a Right Shift Logic circuit (32) before being added to a product of the two multiplicands. An accumulated product of the multiplication function is formed by an adder (36) and shifted to the left by a Left Shift Logic circuit (38) until the accumulated product is in integer form. Implementing an integer multiplication operation with a fractional multiplier in the data processing system requires a single software instruction.
    Type: Grant
    Filed: April 2, 1991
    Date of Patent: November 8, 1994
    Assignee: Motorola, Inc.
    Inventors: Joseph P. Gergen, Peter A. Percosan