Abstract: According to one embodiment, a method for processing one or more X-ray images includes: receiving at least one image of the one or more X-ray images, the one or more X-ray images being of an assembly extending along a plane; based on the at least one image, autonomously determining a respective displacement value for each of portions of the assembly with respect to one or more directions of the plane, each of the displacement values being determined relative to a respective actual value; storing the displacement values; and applying a rule to the stored displacement values, the rule being for determining a defect status of the assembly.

Abstract: According to one embodiment, a calibration system for calibrating image data produced by an imaging system is provided. The calibration system includes a processor configured for: receiving the image data from the imaging system; receiving a plurality of reference values from the imaging system; and calibrating the image data using the reference values. The reference values correspond to air image data produced by the imaging system.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates with a plurality of processors via a plurality of processor busses. Each of the processors can run a separate instance of test software without interfering with software running on any other of the processors. The inventive protocol can be embodied essentially in hardware that can be adapted to an existing infrastructure without requiring substantial modifications of existing hardware or software.

Abstract: According to one embodiment, a system for linearizing image data corresponding to one or more objects and output by an imaging device is provided. The system includes a processor configured for: receiving the image data from the imaging device; and producing a generally linear relationship between the image data and a thickness of the one or more objects. The generally linear relationship is produced according to the equation I = I o ? ? u l ? l . I is an intensity of the image data, I0 is an intensity of energy produced by the imaging device for outputting the image data, ? is an attenuation coefficient of the one or more objects, and l is the thickness of the one or more objects.

Abstract: According to one embodiment, a calibration system for calibrating image data produced by an imaging system is provided. The calibration system includes a processor configured for: receiving the image data from the imaging system; receiving a plurality of reference values from the imaging system; and calibrating the image data using the reference values. The reference values correspond to air image data produced by the imaging system.

Abstract: According to one embodiment, a system for linearizing image data corresponding to one or more objects and output by an imaging device is provided. The system includes a processor configured for: receiving the image data from the imaging device; and producing a generally linear relationship between the image data and a thickness of the one or more objects. The generally linear relationship is produced according to the equation I = I o ? ? - ? l ? l . I is an intensity of the image data, I0 is an intensity of energy produced by the imaging device for outputting the image data, ? is an attenuation coefficient of the one or more objects, and l is the thickness of the one or more objects.

Abstract: According to one embodiment, a method for processing one or more X-ray images includes: receiving at least one image of the one or more X-ray images, the one or more X-ray images being of an assembly extending along a plane; based on the at least one image, autonomously determining a respective displacement value for each of portions of the assembly with respect to one or more directions of the plane, each of the displacement values being determined relative to a respective actual value; storing the displacement values; and applying a rule to the stored displacement values, the rule being for determining a defect status of the assembly.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: A tester having a fast but flexible pattern generator which is implemented using readily available memories. The tester includes a pattern memory which holds test vectors. The vectors are organized into modules. The order of execution of the modules is selected from a list stored in memory. In the preferred embodiment, memories which operate in burst mode are used to implement the pattern memory. To compensate for the decrease in data rate which occurs when execution switches between modules in the middle of a burst, the memory refresh rate is dynamically altered upon switching between modules.

Abstract: Fast loading of a vector test pattern in a semiconductor device tester. Fast loading is achieved through the use of delta coding of vectors in conjunction with a vector cache in the vector loading circuitry of the tester. In this way, the total amount of information transmitted during the loading operation is reduced. Hardware required to implement the method is minimized by using random access memory conventionally found in automatic test equipment for the vector cache.

Abstract: Apparatus and method for detecting timing hazards which might be introduced in a pattern for execution on a tester when edges are improperly programmed in the pattern. The apparatus includes hazard detection circuits associated with the pins of the tester. Each circuit receives control inputs which specify which edges are involved in the hazard and limits on the permissible time between the specified edges. In operation, the pattern is executed repeatedly, once for each hazard which must be detected. The programmed times for the selected edge as well as the drive and format for each period of the pattern are variable inputs to the circuit.

Abstract: Automatic test equipment with a programmable timing generator. In the timing generator, the required delay is split into a course delay, a frequency adjustment delay, and a fine delay. The fine delays for successive cycles are temporarily stored. As the course delays pass, the fine delays are retrieved and used to generate edge signals. The frequency adjustment delay is used to offset the time at which the fine delay is retrieved by a fraction of a the resolution of the course delay. This arrangement allows the fine delay values to be retrieved at a higher rate than the rate at which the signals representing the required delays were generated. With this arrangement, the edges can be generated in a high frequency burst mode even though much of the timing generator is implemented with circuitry that has a lower operating frequency. A significant cost savings results by providing high frequency operation with less expensive components of lower operating frequency.

Abstract: A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit having a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.

Abstract: A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit has a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.

Abstract: An apparatus for processing failure information received from a node of a circuit under test. The apparatus includes a fail processor which receives test data from a node and generates failure data based upon the test data, a plurality of fail memories, each memory being configured to receive and store certain fail data, and a sequence memory configured-to store sequence information indicating in what order the failure data is stored in the plurality of fail memories.

Abstract: "The present invention provides an interpolator circuit including a register, a pulse swallower, a ramping circuit and a compare circuit. The interpolator may be employed in a high speed timing generator".