Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget.

Abstract: An apparatus is described that is used to load containers with small objects similar to Flash memory SD or micro SD cards. The apparatus can be made in three configurations; a fully manual operated configuration, a manual configuration in combination with one or more automated machines, and finally as a fully automated handling apparatus. In its simplest form, the apparatus consists of a base plate with an attached bar containing a grooved bar member such that the jewel cases are restrained in the grooved bar member in such a way as to allow the jewel cases to be moved in a linear or circular direction and provide means such that the cases can be easily loaded with the objects and then removed from the base plate.

Abstract: A memory card in accordance with the present invention allows a variety of memory devices to interface with a processor. The memory card comprises a data base which contains information about the variety of memory devices that are on the card and dual signal pairs that can be used to form different signal sets that are required to test or program the variety of memory devices. The memory card further comprises a plurality of reserved lines that can be used to form additional signal sets and a plurality memory areas. A memory card in accordance with the present invention comprises four different signal groups which allows memory modules that individually contain multiple memory types to be interfaced to a standard CPU. Such a memory bus is referred to as an X-Bus and the memory modules are referred to as X-Cards. The four signal groups of the X-Bus/X-Card combination are described below. 1.