Abstract: A non-transitory device-readable medium, which may be embodied in a device, such as a radar receiver, stores instructions that, when executed by processing circuitry, are configured to perform operations to identify a region of interference. An analog signal is generated based on received signals reflected from a target object and an interfering object. The analog signal is converted to an initial time-domain data set. Processing circuitry is configured or instructed to perform a transform operation on the initial time-domain data set to generate a frequency-domain data set, based on which a region of interference may be identified. Subsequent operations may be performed to facilitate identification of the region of interest including thresholding, inverse transforming, subtracting, and/or combining. The processing circuitry may be further configured or instructed to generate repaired time-domain data from which corrupted time-domain samples to remove data associated with the interfering object.

Abstract: A non-transitory device-readable medium, which may be embodied in a device, such as a radar receiver, stores instructions that, when executed by processing circuitry, are configured to perform operations to identify a region of interference. An analog signal is generated based on received signals reflected from a target object and an interfering object. The analog signal is converted to an initial time-domain data set. Processing circuitry is configured or instructed to perform a transform operation on the initial time-domain data set to generate a frequency-domain data set, based on which a region of interference may be identified. Subsequent operations may be performed to facilitate identification of the region of interest including thresholding, inverse transforming, subtracting, and/or combining. The processing circuitry may be further configured or instructed to generate repaired time-domain data from which corrupted time-domain samples to remove data associated with the interfering object.

Abstract: A method is provided. In some examples, the method includes performing, by processing circuitry, a first transform operation on a first time-domain data set to generate a frequency-domain data set. In addition, the method includes determining, by the processing circuitry, that at least one portion of the frequency-domain data set satisfies a first threshold magnitude. The method also includes performing, by the processing circuitry, an inverse transform operation on the at least one portion of the frequency-domain data set to generate a second time-domain data set. The method further includes identifying, by the processing circuitry and based on the second time-domain data set, a region of interference in the first time-domain data set.

Abstract: A method is provided. In some examples, the method includes performing, by processing circuitry, a first transform operation on a first time-domain data set to generate a frequency-domain data set. In addition, the method includes determining, by the processing circuitry, that at least one portion of the frequency-domain data set satisfies a first threshold magnitude. The method also includes performing, by the processing circuitry, an inverse transform operation on the at least one portion of the frequency-domain data set to generate a second time-domain data set. The method further includes identifying, by the processing circuitry and based on the second time-domain data set, a region of interference in the first time-domain data set.

Abstract: A circuit includes a buffer, a first programmable real-time unit (PRU), and a second PRU. The first PRU is coupled to the buffer and configured to couple to an input interface. The first PRU is further configured to receive first data sampled by the input interface and receive second data sampled by the input interface. The first PRU is further configured to multiplex the first data and the second data to generate multiplexed data and transmit the multiplexed data to the buffer. The second PRU is coupled to the buffer and configured to couple to an output interface. The second PRU is further configured to obtain the multiplexed data from the buffer and transmit the multiplexed data via an Ethernet physical layer.

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method comprises sampling a first data interface to generate a first data sample. The method further comprises sampling a second data interface to generate a second data sample. The method further comprises combining the first data sample and the second data sample to generate combined data. The method further comprises transmitting the combined data on a sample basis at an Ethernet physical layer of communication.

Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.

Abstract: A device is provided that includes a processor, a flash memory configured to store error correcting code (ECC) blocks for execution in place (XIP) processing by the processor, wherein an ECC block includes a data block and an ECC code for the data block, a flash interface controller coupled to the flash memory, and an error correcting code (ECC) engine coupled between the processor and the flash interface controller, wherein the ECC engine is configured to receive a read command for the flash memory from the processor, to translate a read address to an ECC block address, to read the ECC block at the ECC block address from the flash memory via the flash interface controller, and to verify the ECC code in the read ECC block.

Abstract: A system for collection, containment, and disposal of contaminated fluids includes a flexible hulled containment vessel having at least one resilient deformable wall and a flow directing apparatus with a body that extends into the containment vessel during use, and an exterior portal that extends from the containment vessel in use. The flow directing apparatus provides fluid communication from an interior of the containment vessel while resisting collapse of the deformable wall during removal of contaminated fluid therefrom. A body of the flow directing apparatus includes side wall apertures spaced along a length thereof, sized to accommodate solids expected to be in the contaminated fluids. Bridge structures help resist collapse. A diameter of the body may be larger than a diameter of the exterior portal, which may further resist collapse. The containment vessel may be foldable for transport or storage.

Abstract: A system for collection, containment, and disposal of contaminated fluids includes a flexible hulled containment vessel having at least one resilient deformable wall and a flow directing apparatus with a body that extends into the containment vessel during use, and an exterior portal that extends from the containment vessel in use. The flow directing apparatus provides fluid communication from an interior of the containment vessel while resisting collapse of the deformable wall during removal of contaminated fluid therefrom. A body of the flow directing apparatus includes side wall apertures spaced along a length thereof, sized to accommodate solids expected to be in the contaminated fluids. Bridge structures help resist collapse. A diameter of the body may be larger than a diameter of the exterior portal, which may further resist collapse. The containment vessel may be foldable for transport or storage.

Abstract: Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiver unit (30) for the reception of the data and a transmitter unit (22) for the transmission of data. The output of a data value by the transmitter unit (22) of one module (12) to another module (10) at the serial data bus (18), and the import of the data value by the receiver unit (30) of the corresponding other module (10) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module (12) is delayed via a delay element (38) one pulse repetition period (?TP) of the clock signal (CLK).

Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.

Abstract: Method and apparatus for serial data transfer between at least two modules (10, 12) connected to each other by way of a serial data bus (18) where the data transfer is governed by a clock signal (CLK). The modules (10, 12) each comprise a receiver unit (30) for the reception of the data and a transmitter unit (22) for the transmission of data. The output of a data value by the transmitter unit (22) of one module (12) to another module (10) at the serial data bus (18), and the import of the data value by the receiver unit (30) of the corresponding other module (10) are initiated by slopes of the clock signal (CLK). The clock signal that triggers the transmission of this data value in the one module (12) is delayed via a delay element (38) one pulse repetition period (ATP) of the clock signal (CLK).

Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.