Patents by Inventor Peter B. Gray

Peter B. Gray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10367083
    Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik, Alvin J. Joseph, Peter B. Gray
  • Publication number: 20190181250
    Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.
    Type: Application
    Filed: February 18, 2019
    Publication date: June 13, 2019
    Inventors: Vibhor Jain, Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik, Alvin J. Joseph, Peter B. Gray
  • Publication number: 20170278955
    Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 28, 2017
    Inventors: Vibhor Jain, Renata Camillo-Castillo, Qizhi Liu, John J. Pekarik, Alvin J. Joseph, Peter B. Gray
  • Patent number: 9318584
    Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peng Cheng, Peter B. Gray, Vibhor Jain, Robert K. Leidy, Qizhi Liu
  • Patent number: 9231087
    Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
  • Publication number: 20150214344
    Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
    Type: Application
    Filed: April 2, 2015
    Publication date: July 30, 2015
    Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
  • Patent number: 9059196
    Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: John J. Benoit, James R. Elliot, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
  • Publication number: 20150123245
    Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: International Business Machines Corporation
    Inventors: John J. Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Qizhi Liu, Christa R. Willets
  • Publication number: 20150041956
    Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.
    Type: Application
    Filed: September 22, 2014
    Publication date: February 12, 2015
    Inventors: Peng Cheng, Peter B. Gray, Vibhor Jain, Robert K. Leidy, Qizhi Liu
  • Patent number: 8921195
    Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Peng Cheng, Peter B. Gray, Vibhor Jain, Robert K. Leidy, Qizhi Liu
  • Patent number: 8810005
    Abstract: A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, Peng Cheng, Peter B. Gray, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 8716837
    Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Peter B. Gray, David L. Harame, Alvin J. Joseph, Marwan H. Khater, Qizhi Liu
  • Publication number: 20140117493
    Abstract: Methods for fabricating a device structure, as well as device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Cheng, Peter B. Gray, Vibhor Jain, Robert K. Leidy, Qizhi Liu
  • Patent number: 8710500
    Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Erik M. Dahlstrom, Peter B. Gray, David L. Harame, Qizhi Liu
  • Patent number: 8536012
    Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Peter B. Gray, David L. Harame, Alvin J. Joseph, Marwan H. Khater, Qizhi Liu
  • Patent number: 8513706
    Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Erik M. Dahlstrom, Peter B. Gray, Qizhi Liu
  • Patent number: 8492237
    Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Erik M. Dahlstrom, Peter B. Gray, David L. Harame, Qizhi Liu
  • Patent number: 8482101
    Abstract: A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: John J. Benoit, Mattias E. Dahlstrom, Mark D. Dupuis, Peter B. Gray, Anthony K. Stamper
  • Patent number: 8405186
    Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Mattias E. Dahlstrom, Peter B. Gray, David L. Harame, Russell T. Herrin, Alvin J. Joseph, Andreas D. Stricker
  • Patent number: 8389372
    Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: March 5, 2013
    Assignee: International Business Machines Corporation
    Inventors: Erik M. Dahlstrom, Peter B. Gray, Qizhi Liu