Abstract: A method and device for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner is provided. A marking signal is produced, indicating a predefined circuit state that might occur in specific components of an electric circuit, wherein a transformed network list is formed from an original network list describing the circuit, whereby all electric components of at least one predefined component group, with regard to a respective connection pair, are treated as short-circuited, all network nodes connected by one or several components that are to be treated as short-circuited are respectively combined to form an equivalence category, wherein respectively all states of the associated network nodes are assigned to each equivalence category, it is possible to determine whether and in which components the predefined circuit state can occur by taking into account the equivalence categories.

Abstract: A method and device for testing an electrical circuit, which do not require a thorough electrical circuit simulation but reliably identifying circuit faults. Preferred embodiments generate a fault signal that indicates that a given state of the circuit, which is defined by an electrical state variable, could occur in an electrical circuit. Generally, electrical components are individually treated as short-circuited or non-conducting regarding each pair of connections of the components. An electrical state variable is permanently allocated to at least one network node or a connecting pin of the electrical circuit. Electrical state variables of the network nodes and connecting pins of the components that are to be treated as short-circuited are allocated to each network node and each connecting pin. An assessment is made at least based on the allocated state variables as to whether the given circuit state can occur.

Abstract: A method for analyzing an integrated circuit (or constituent parts thereof), a computer program implementing the method, and a computer configured to execute the program is disclosed. Analyzing the integrated circuit may include retrieving a design for the integrated circuit from a layout database, identifying the bond pads and gates included in the design of the integrated circuit, determining the connections between the bond pads and the gates, and determining whether a connection between a particular gate and a particular bond pad lacks a connection segment routed over a required layer.

Abstract: A method and device for testing an electric circuit, wherein exhaustive electric circuit modulation is not required yet circuit errors can be recognized in a reliable manner is provided. A marking signal is produced, indicating a predefined circuit state that might occur in specific components of an electric circuit, wherein a transformed network list is formed from an original network list describing the circuit, whereby all electric components of at least one predefined component group, with regard to a respective connection pair, are treated as short-circuited, all network nodes connected by one or several components that are to be treated as short-circuited are respectively combined to form an equivalence category, wherein respectively all states of the associated network nodes are assigned to each equivalence category, it is possible to determine whether and in which components the predefined circuit state can occur by taking into account the equivalence categories.

Abstract: A method and device for testing an electrical circuit, which do not require a thorough electrical circuit simulation but reliably identifying circuit faults. Preferred embodiments generate a fault signal that indicates that a given state of the circuit, which is defined by an electrical state variable, could occur in an electrical circuit. Generally, electrical components are individually treated as short-circuited or non-conducting regarding each pair of connections of the components. An electrical state variable is permanently allocated to at least one network node or a connecting pin of the electrical circuit. Electrical state variables of the network nodes and connecting pins of the components that are to be treated as short-circuited are allocated to each network node and each connecting pin. An assessment is made at least based on the allocated state variables as to whether the given circuit state can occur.

Abstract: A method for processing first data representing parameters relating to several components of an electrical circuit provides an associated first data record for each component. The components of the circuit are checked against specific parameters. The parameters relate to the connection of the components to networks, or to electrical/geometric characteristics of the components. The check of the “basic rules” results in the formation of binary values. The binary values are then logically linked to check an “overall rule”. One such overall rule is, for example, the rule for checking the circuit for adequate electrostatic discharge (ESD) protection. A computer readable storage medium and a data processing system, each containing computer-executable instructions for performing the method, are provided.

Abstract: An integrated electric circuit includes one or more circuit networks each having a large number of circuit elements. Images of circuit networks are produced on a computer system and checked for correctness by using predefined testing rules. Those images are marked in which at least one fault is determined. The information obtained in this way is output.

Abstract: A layout of an integrated electrical circuit on a memory unit of a computer system includes one or more instantiations of at least one circuit network description as well as information about the instantiations. A raw data structure represents the logical configuration of the layout and associates each instantiation with one, and only one, polygon data structure. A modified data structure is produced to represent the layout, which associates a circuit network description with one, and only one, polygon data structure, wherein the geometrical differences between the instantiations of this circuit network description are taken into account by variants in the polygon data structure.

Abstract: A layout of an integrated electrical circuit on a memory unit of a computer system includes one or more instantiations of at least one circuit network description as well as information about the instantiations. A raw data structure represents the logical configuration of the layout and associates each instantiation with one, and only one, polygon data structure. A modified data structure is produced to represent the layout, which associates a circuit network description with one, and only one, polygon data structure, wherein the geometrical differences between the instantiations of this circuit network description are taken into account by variants in the polygon data structure.

Abstract: A method for processing first data representing parameters relating to several components of an electrical circuit provides an associated first data record for each component. The components of the circuit are checked against specific parameters. The parameters relate to the connection of the components to networks, or to electrical/geometric characteristics of the components. The check of the “basic rules” results in the formation of binary values. The binary values are then logically linked to check an “overall rule”. One such overall rule is, for example, the rule for checking the circuit for adequate electrostatic discharge (ESD) protection. A computer readable storage medium and a data processing system, each containing computer-executable instructions for performing the method, are provided.

Abstract: A method for processing data containing information about an electronic circuit having a plurality of hierarchically organized networks is disclosed. The method involves processing the data which represent the circuit to be tested such that all the networks of the circuit are checked in hierarchical order for an association with a network type. If such an association is established, it is transferred to the data record for the network at the top of the hierarchy (i.e., top network). The association is then transferred to the data records for the subnetworks associated with the top network (in the opposite hierarchical order). The knowledge of the association between each network and the network type can then be used for a plausibility check of the circuit. Further, a computer readable storage medium and a data processing system contain computer-executable instructions for performing the method.

Abstract: A method for checking electrical networks, in which the geometric characteristics of all the components in the network are checked. Components that have predetermined geometric characteristics are marked. A test is then carried out to determine whether the marked components are disposed at required points in the network, that is to say whether they are interconnected as required. Conversely, it is also possible to check the interconnection of the components in the network, to mark the components with the required interconnection, and then to check whether they also have the required geometric characteristics.

Abstract: An integrated electric circuit includes one or more circuit networks each having a large number of circuit elements. Images of circuit networks are produced on a computer system and checked for correctness by using predefined testing rules. Those images are marked in which at least one fault is determined. The information obtained in this way is output.