Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract: When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

Abstract: The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing an O2 flash while shaping gate spacers, and then cleaning and applying a second application of Aqua Regia. Embodiments include sputter depositing a layer of Ni/Pt on a semiconductor substrate, annealing the Ni/Pt layer, wet stripping unreacted Ni, annealing the Ni stripped Ni/Pt layer, stripping unreacted Pt from the annealed Ni/Pt layer, e.g., with Aqua Regia, treating the Pt stripped Ni/Pt layer with an oxygen plasma, cleaning the Ni/Pt layer, and stripping unreacted Pt from the cleaned Ni/Pt layer, e.g., with a second application of Aqua Regia.

Abstract: An integrated circuit device includes a PMOS transistor and an NMOS transistor. The PMO transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the PMOS transistor, and a multi-part second sidewall spacer positioned adjacent the first sidewall spacer of the PMOS transistor, wherein the multi-part second sidewall spacer includes an upper spacer and a lower spacer. The NMOS transistor includes a gate electrode, at least one source/drain region, a first sidewall spacer positioned adjacent the gate electrode of the NMOS transistor, and a single second sidewall spacer positioned adjacent the first sidewall spacer of the NMOS transistor. A metal silicide region is positioned on each of the gate electrodes and on each of the at least one source/drain regions of the PMOS and the NMOS transistors.

Abstract: The present disclosure is directed to various methods of forming metal silicide regions on an integrated circuit device. In one example, the method includes forming a PMOS transistor and an NMOS transistor, each of the transistors having a gate electrode and at least one source/drain region formed in a semiconducting substrate, forming a first sidewall spacer adjacent the gate electrodes and forming a second sidewall spacer adjacent the first sidewall spacer.

Abstract: Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.

Abstract: When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.

Abstract: When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.

Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.

Abstract: A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions.

Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract: Disclosed herein are various methods of forming replacement gate structures and conductive contacts on semiconductor devices and devices incorporating the same. One exemplary device includes a plurality of gate structures positioned above a semiconducting substrate, at least one sidewall spacer positioned proximate respective sidewalls of the gate structures, and a metal silicide region in a source/drain region of the semiconducting substrate, the metal silicide region extending laterally so as to contact the sidewall spacer positioned proximate each of the gate structures.

Abstract: Methods are provided for forming semiconductor devices. One method includes etching trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. Dummy gate structures are formed, which includes a first dummy gate structure, that overlie and are transverse to the fins. A back fill material is filled between the dummy gate structures. The first dummy gate structure and an upper portion of the insulating material are removed to expose an active fins portion of the fins. The active fins portion is dimensionally modified to form an altered active fins portion. A high-k dielectric material and a work function determining gate electrode material are deposited overlying the altered active fins portion.

Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.

Abstract: An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.

Abstract: Disclosed herein is an illustrative semiconductor device that includes a transistor having drain and source regions and a gate electrode structure. The disclosed semiconductor device also includes a contact bar formed in a first dielectric material that connects to one of the drain and source regions and includes a first conductive material, the contact bar extending along a width direction of the transistor. Moreover, the illustrative device further includes, among other things, a conductive line formed in a second dielectric material, the conductive line including an upper portion having a top width extending along a length direction of the transistor and a lower portion having a bottom width extending along the length direction that is less than the top width of the upper portion, wherein the conductive line connects to the contact bar and includes a second conductive material that differs from the first conductive material.

Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer.

Abstract: A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.

Abstract: When forming substrate diodes in SOI devices, superior diode characteristics may be preserved by providing an additional spacer element in the substrate opening and/or by using a superior contact patterning regime on the basis of a sacrificial fill material. In both cases, integrity of a metal silicide in the substrate diode may be preserved, thereby avoiding undue deviations from the desired ideal diode characteristics. In some illustrative embodiments, the superior diode characteristics may be achieved without requiring any additional lithography step.