Patents by Inventor Peter Baars

Peter Baars has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250239450
    Abstract: Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer including a first section and a second section adjacent to the first section, a second semiconductor layer including a section and a semiconductor region that projects from the second section of the first semiconductor layer to the section of the second semiconductor layer, and a dielectric layer disposed between the first section of the first semiconductor layer and the section of the second semiconductor layer. The section and the semiconductor region of the second semiconductor layer comprise one or more single-crystal semiconductor materials.
    Type: Application
    Filed: January 24, 2024
    Publication date: July 24, 2025
    Inventors: Judson R. Holt, Kaushikee Mishra, Kenneth J. Giewont, Mohnish Manghnani, Jonathan McCutcheon, Peter Baars
  • Publication number: 20250227999
    Abstract: Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Inventors: Peter Baars, Halid Mulaosmanovic, Zhixing Zhao
  • Publication number: 20250228009
    Abstract: Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Inventors: Zhixing Zhao, Halid Mulaosmanovic, Peter Baars
  • Publication number: 20250227943
    Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.
    Type: Application
    Filed: January 10, 2024
    Publication date: July 10, 2025
    Inventors: Alexander Derrickson, Halid Mulaosmanovic, Peter Baars, Judson R. Holt, Zhixing Zhao
  • Publication number: 20250159913
    Abstract: Embodiments of the disclosure provide a structure including a first emitter/collector (E/C) layer over a substrate. A base structure is over the substrate and adjacent a first horizontal end of the first E/C layer. A bounding structure is over the substrate and adjacent a second horizontal end of the first E/C layer. The bounding structure, in some implementations, may include a gate conductor or a base material. A spacer is between the first E/C layer and the bounding structure.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 15, 2025
    Inventors: Judson Robert Holt, Peter Baars, Alexander M. Derrickson
  • Publication number: 20250159905
    Abstract: Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 15, 2025
    Inventors: Halid Mulaosmanovic, Peter Baars
  • Patent number: 12113070
    Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 8, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Peter Baars, Viorel Ontalus, Ketankumar H. Tailor, Michael Zier, Crystal R. Kenney, Judson Holt
  • Patent number: 11916109
    Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: February 27, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Peter Baars, Alexander M. Derrickson, Ketankumar Harishbhai Tailor, Zhixing Zhao, Judson R. Holt
  • Patent number: 11888062
    Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: January 30, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Felix Holzmüller, Ruchil K. Jain, Peter Baars
  • Publication number: 20230395607
    Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventors: Peter Baars, Viorel Ontalus, Ketankumar H. Tailor, Michael Zier, Crystal R. Kenney, Judson Holt
  • Publication number: 20230290829
    Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 14, 2023
    Inventors: Peter Baars, Alexander M. Derrickson, Ketankumar Harishbhai Tailor, Zhixing Zhao, Judson R. Holt
  • Patent number: 11705455
    Abstract: The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: July 18, 2023
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Thorsten E. Kammler, Peter Baars
  • Publication number: 20230106168
    Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 6, 2023
    Inventors: Felix Holzmüller, Ruchil K. Jain, Peter Baars
  • Patent number: 11532742
    Abstract: An integrated circuit (IC) structure and a field plate are disclosed. The IC structure and field plate may find advantageous application with, for example, extended drain metal-oxide semiconductor (EDMOS) transistors. The IC structure includes a transistor including a metal gate structure and a drain extension region extending laterally from partially under the metal gate structure to a drain region. A metal field plate is over the drain extension region. Due to being formed simultaneously as part of a gate-last formation approach, the metal field plate has an upper surface coplanar with an upper surface of the metal gate structure. A field plate contact may be on the metal field plate.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 20, 2022
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Ketankumar Harishbhai Tailor, Peter Baars
  • Patent number: 11456364
    Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: September 27, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Ketankumar H. Tailor, Peter Baars, Ruchil K. Jain
  • Publication number: 20220302306
    Abstract: An integrated circuit (IC) structure and a field plate are disclosed. The IC structure and field plate may find advantageous application with, for example, extended drain metal-oxide semiconductor (EDMOS) transistors. The IC structure includes a transistor including a metal gate structure and a drain extension region extending laterally from partially under the metal gate structure to a drain region. A metal field plate is over the drain extension region. Due to being formed simultaneously as part of a gate-last formation approach, the metal field plate has an upper surface coplanar with an upper surface of the metal gate structure. A field plate contact may be on the metal field plate.
    Type: Application
    Filed: March 19, 2021
    Publication date: September 22, 2022
    Inventors: Ketankumar Harishbhai Tailor, Peter Baars
  • Patent number: 11289598
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to co-integrated high voltage and medium voltage devices and methods of manufacture. The structure includes a substrate having a semiconductor on insulator (SOI) region and a bulk region; and a first device formed on the bulk region, the first device having a first gate dielectric layer and a second gate dielectric layer surrounding the first dielectric layer, and a thickness of the first gate dielectric layer and the second gate dielectric layer being greater than a thickness of an insulator layer of the SOI region.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 29, 2022
    Assignee: GLOBALFOUNDRIES DRESDEN MODULE ONE LIMITED LIABILITY COMPANY & CO. KG
    Inventors: Nan Wu, Thorsten E. Kammler, Peter Baars
  • Publication number: 20220093751
    Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: Ketankumar H. Tailor, Peter Baars, Ruchil K. Jain
  • Patent number: 11217678
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: January 4, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: George Robert Mulfinger, Ryan Sporer, Rick J. Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel
  • Patent number: 11195935
    Abstract: A semiconductor device is disclosed including a gate electrode structure and raised drain and source regions that extend to a first height level and a sidewall spacer element positioned adjacent the sidewalls of the gate electrode structure between the raised drain and source regions and the gate electrode structure. The sidewall spacer element includes an upper portion that extends above the first height level wherein an inner part of the spacer element faces the gate electrode structure and extends to a second height level that is less than a third height level of an outer part of the upper portion of the spacer element.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: December 7, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hans-Juergen Thees, Peter Baars