Abstract: A semiconductor device includes a semiconductor substrate, a channel disposed over the semiconductor substrate and extending in a specific direction, a drain disposed at a first end of the channel, a source disposed at a second end of the channel, and a gate disposed over the channel and configured to control a current through the channel. The gate, or the channel, or both include a semiconductor material that is monocrystalline.

Abstract: A wind turbine rotor blade has a base plate having an access opening, and having a cover via which the access opening can be closed. A holding arrangement is configured such that a movement of the cover relative to the base plate in a predetermined direction parallel to the plane of the base plate causes the cover to be held in a form-fitting manner on the base plate, and a locking device blocks a movement of the cover in a direction opposite to the predetermined direction.

Abstract: Structures that include an isotopically-depleted semiconductor layer and methods of forming such structures. The structure comprises a semiconductor layer comprising a semiconductor material having an isotope with a concentration that is less than a natural abundance of the first isotope and greater than zero parts per million.

Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a ferroelectric material. A structure of the disclosure may include a base over a substrate. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion. A ferroelectric spacer is adjacent the second portion of the base. Other structures include a ferroelectric layer over a back gate terminal of a substrate. A base is on the ferroelectric layer. The base includes a first portion laterally between an emitter and a collector, and a second portion over the first portion.

Abstract: Structures that include a semiconductor layer formed by lateral epitaxial growth and methods of forming such structures. The structure comprises a first semiconductor layer including a first section and a second section adjacent to the first section, a second semiconductor layer including a section and a semiconductor region that projects from the second section of the first semiconductor layer to the section of the second semiconductor layer, and a dielectric layer disposed between the first section of the first semiconductor layer and the section of the second semiconductor layer. The section and the semiconductor region of the second semiconductor layer comprise one or more single-crystal semiconductor materials.

Abstract: Embodiments of the disclosure provide a crystalline semiconductor layer between a bipolar transistor structure and a field effect transistor (FET) structure. The structure includes a dielectric layer on a back-gate semiconductor layer, a bipolar transistor structure on the dielectric layer, FET structure on the dielectric layer, and a crystalline semiconductor layer on the dielectric layer between the bipolar transistor structure and the FET structure. The crystalline semiconductor layer includes a terminal of the bipolar transistor structure and a terminal of the FET structure.

Abstract: Embodiments of the disclosure provide a structure including a first back-gate well adjacent a second back-gate well. A bipolar transistor (BT) is over the first back-gate well and includes a base structure laterally between a set of emitter/collector (E/C) terminals and extending longitudinally away from the set of E/C terminals. A field effect transistor (FET) is over the second back-gate well and includes a gate structure laterally between a set of source/drain (S/D) terminals and extending longitudinally away from the set of S/D terminals toward the BT. The gate structure is coupled to the base structure.

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. The structure comprises a first semiconductor layer including a first portion, a second portion, and a third portion between the first portion and the second portion, a first terminal including a first semiconductor region on the first portion of the first semiconductor layer, a second terminal including a second semiconductor region on the second portion of the first semiconductor layer, an intrinsic base laterally disposed between the first terminal and the second terminal, and an extrinsic base on the intrinsic base. The intrinsic base includes a doped region in the third portion of the first semiconductor layer, and the doped region has a dopant depth profile with a dopant concentration that is asymmetrical relative to the first terminal and the second terminal.

Abstract: Embodiments of the disclosure provide a structure including a first emitter/collector (E/C) layer over a substrate. A base structure is over the substrate and adjacent a first horizontal end of the first E/C layer. A bounding structure is over the substrate and adjacent a second horizontal end of the first E/C layer. The bounding structure, in some implementations, may include a gate conductor or a base material. A spacer is between the first E/C layer and the bounding structure.

Abstract: Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to quantum dot structures and methods of manufacture. The structure includes: a plurality of barrier gates; a plurality of spin qubit gates interdigitated with the plurality of barrier gates; and access gates on opposing sides of the plurality of barrier gates.

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.

Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

Abstract: The present disclosure relates to semiconductor devices, and more particularly, to high voltage extended drain MOSFET (EDMOS) devices in a high-k metal gate (HKMG) and methods of manufacture. A structure of the present disclosure includes a plurality of extended drain MOSFET (EDMOS) devices on a high voltage well with a split-gate dielectric material including a first gate dielectric material and a second gate dielectric material, the second gate dielectric material including a thinner thickness than the first gate dielectric material, and a high-k dielectric material on the split-gate dielectric material.

Abstract: Structures for an extended-drain metal-oxide-semiconductor device and methods of forming a structure for an extended-drain metal-oxide-semiconductor device. The structure includes a semiconductor substrate containing a first semiconductor material, a source region and a drain region in the semiconductor substrate, a gate electrode positioned in a lateral direction between the source region and the drain region, and a semiconductor layer positioned on the semiconductor substrate. The semiconductor layer contains a second semiconductor material that differs in composition from the first semiconductor material. The gate electrode includes a first section positioned in a vertical direction over the semiconductor layer and a second section positioned in the vertical direction over the semiconductor substrate.

Abstract: An integrated circuit (IC) structure and a field plate are disclosed. The IC structure and field plate may find advantageous application with, for example, extended drain metal-oxide semiconductor (EDMOS) transistors. The IC structure includes a transistor including a metal gate structure and a drain extension region extending laterally from partially under the metal gate structure to a drain region. A metal field plate is over the drain extension region. Due to being formed simultaneously as part of a gate-last formation approach, the metal field plate has an upper surface coplanar with an upper surface of the metal gate structure. A field plate contact may be on the metal field plate.

Abstract: Embodiments of the disclosure provide an integrated circuit device and related methods. The disclosure may provide a transistor device, including: a gate structure; a drain extension region extending laterally from partially under the gate structure to a drain region; and a gate spacer located over the drain extension region. A silicide-blocking layer is over and in contact with the gate spacer. The silicide-blocking layer has a first end over the gate structure and a second, opposing end over the drain extension region. The structure also provides a conductive field plate, including a conductive layer over and in contact with the silicide-blocking layer. A field plate contact is formed on the conductive field plate.