Abstract: The present disclosure generally relates to a conductive perforated plate for electrical testing of a device under test (DUT) in semiconductor processing. In an example, a device circuit in a die area is formed in or over a semiconductor substrate. The device circuit has an interconnect level. A DUT is formed in or over the semiconductor substrate. A conductive perforated plate is formed in the interconnect level conductively connected to the DUT. A plurality of insulating islands is disposed within the conductive perforated plate.

Abstract: In examples, a semiconductor package comprises a bond pad surface layer, a second conductive layer positioned below the bond pad surface layer, and a perforated plate positioned between and abutting the bond pad surface layer and the second conductive layer. The perforated plate has a monolithic conductive member and multiple insulation members embedded within the conductive member, the insulation members having thicknesses approximately equivalent to that of the conductive member. The package also includes a semiconductor substrate including a circuit, the semiconductor substrate positioned below the second conductive layer.

Abstract: The instant invention provides pharmaceutical formulations for a long acting injectable drug product comprising a suspension of doravirine for parenteral administration via intramuscular or subcutaneous routes. The drug product can be used for the treatment or prophylaxis of infection by HIV or for the treatment, prophylaxis, or delay in the onset of AIDS (acquired immunodeficiency syndrome) or ARC (AIDS related complex).

Abstract: The instant invention provides pharmaceutical formulations for a long acting injectable drug product comprising a suspension of doravirine for parenteral administration via intramuscular or subcutaneous routes. The drug product can be used for the treatment or prophylaxis of infection by HIV or for the treatment, prophylaxis, or delay in the onset of AIDS (acquired immunodeficiency syndrome) or ARC (AIDS related complex).

Abstract: In a method suitable for processing colour values provided by a camera sensor comprising pixels of different colours, values of a first colour at positions of pixels of a second and a third colour are interpolated (102) based on an averaging using at least one control value.

Abstract: Voltage regulator with an output transistor MP1, including a first PMOS FET, whereby the input voltage Vdd of the voltage regulator is applied to the source of the output transistor MP1 and where the drain of the output transistor MP1 constitutes the output of the voltage regulator. The voltage regulator, furthermore, includes a regulation circuit 1 that may, for example, consist of an error amplifier and that controls the output transistor in such a way that the least possible deviations between the output voltage Vout and the target output voltage are allowed to occur.

Abstract: Voltage regulator with an output transistor MP1, including a first PMOS FET, whereby the input voltage Vdd of the voltage regulator is applied to the source of the output transistor MP1 and where the drain of the output transistor MP1 constitutes the output of the voltage regulator. The voltage regulator, furthermore, includes a regulation circuit 1 that may, for example, consist of an error amplifier and that controls the output transistor in such a way that the least possible deviations between the output voltage Vout and the target output voltage are allowed to occur.

Abstract: The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time.

Abstract: The circuit configuration for the generation of clock signals for a semiconductor memory (14) that are edge-synchronous with the output signals of a clock generator (16) comprises an input stage (20) to which the output signals of the clock generator (16) are applied. It furthermore contains a phase detector (30) which receives the signals output by the input stage (20) and whose output signals control a voltage-controlled oscillator (34) which supplies the clock signals for the semiconductor memory (14). It also contains a conversion stage (42) which applies signals related to the output signals of the oscillator (34) to the phase detector (30), which controls the oscillator in such a way that the phase difference between the signals reaching it from the input stage (20) and the signals also reaching it from the conversion stage (42) becomes zero. The input stage (20) comprises an amplifier (44) containing a circuit component (62) capable of influencing the signal transit time.

Abstract: In a carillon or chimes keyboard, which may be a manual or a pedal set, the eys (sticks or pedals) and the frame for taking them up pivotally are provided with cooperating surfaces, one surface on the key hitting the other surface on the frame at the end of the upward release movement of the key after it has been depressed for operating a bell.For dampening the clattering noise caused by this hitting, the invention provides for such cooperating surfaces on the keys and the frame, which are inclined, preferably at about 30.degree., to the upward direction of movement of the keys just before they hit on the frame during this release movement.