Patents by Inventor Peter Bannon

Peter Bannon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210153868
    Abstract: A system for forming an anastomosis between first and second sections of a digestive tract includes Optical Scope Device (“OSD”) having a lumen extending therethrough and positioned at a first target site within the first section, OSD including an imaging component at a distal end thereof for viewing the first target site; First Endoscope (“FE”) including a working channel extending therethrough and positioned at a second target site within the second section; Capture Device (“CD”) extending from a proximal end to a distal end including a loop, CD extends through the lumen; First Flexible Element (“FFE”) extends through FE, FFE including a coupling element which passes through the loop to couple FFE to CD, connecting the first and second sections, the coupling element moving between insertion and locking configurations; and Stent having a lumen extending therethrough which provides fluid communication between the first and second sections.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: Todd Baron, Peter L. Dayton, Bryan Bannon, Barry Weitzner, Thomas Desimio
  • Publication number: 20200394095
    Abstract: A system for handling errors in a neural network includes a neural network processor for executing a neural network associated with use of a vehicle. The neural network processor includes an error detector configured to detect a data error associated with execution of the neural network and a neural network controller configured to receive a report of the data error from the error detector. In response to receiving the report, the neural network controller is further configured to signal that a pending result of the neural network is tainted without terminating execution of the neural network.
    Type: Application
    Filed: March 30, 2020
    Publication date: December 17, 2020
    Inventors: Christopher Hsiong, Emil Talpes, Debjlt Das Sarma, Peter Bannon, Kevin Hurd, Benjamin Floering
  • Patent number: 10606678
    Abstract: A system for handling errors in a neural network includes a neural network processor for executing a neural network associated with use of a vehicle. The neural network processor includes an error detector configured to detect a data error associated with execution of the neural network and a neural network controller configured to receive a report of the data error from the error detector. In response to receiving the report, the neural network controller is further configured to signal that a pending result of the neural network is tainted without terminating execution of the neural network.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 31, 2020
    Assignee: Tesla, Inc.
    Inventors: Christopher Hsiong, Emil Talpes, Debjit Das Sarma, Peter Bannon, Kevin Hurd, Benjamin Floering
  • Publication number: 20190155678
    Abstract: A system for handling errors in a neural network includes a neural network processor for executing a neural network associated with use of a vehicle. The neural network processor includes an error detector configured to detect a data error associated with execution of the neural network and a neural network controller configured to receive a report of the data error from the error detector. In response to receiving the report, the neural network controller is further configured to signal that a pending result of the neural network is tainted without terminating execution of the neural network.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 23, 2019
    Applicant: Tesla, Inc.
    Inventors: Christopher Hsiong, Emil Talpes, Debjit Das Sarma, Peter Bannon, Kevin Hurd, Benjamin Floering
  • Publication number: 20070113020
    Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.
    Type: Application
    Filed: November 17, 2005
    Publication date: May 17, 2007
    Applicant: P.A. Semi, Inc.
    Inventors: Ramesh Gunna, Sudarshan Kadambi, Peter Bannon