Abstract: A hydraulic lock apparatus, comprising: a lock operator piston arranged to be axially moveable in a piston chamber, the lock operator piston defining a first seal area; a fluid release valve comprising a valve port and a valve member axially moveable within a valve chamber, wherein the fluid release valve is moveable from a sealing arrangement to an open arrangement, wherein the fluid release valve defines a second seal area when in the sealing arrangement; and a hydraulic chamber defined between the first seal area of the lock operator piston and the second seal area of the fluid release valve; wherein the first seal area is larger than the second seal area; and the fluid release valve is configured to be moveable from the sealing arrangement, in which the hydraulic chamber is isolated from the valve port, to the open arrangement, in which the hydraulic chamber is connected to the valve port, in response to a differential pressure cycle being applied to the valve member over the second seal area.

Abstract: A downhole drag reducing apparatus 18 comprises a mandrel 20 and a bearing sleeve 24 mounted on the mandrel 20, such that the mandrel 20 and bearing sleeve 24 are rotatable relative to each other. The bearing sleeve 24 defines a bore wall engaging surface. The apparatus 18 comprises a reciprocating piston 23 mounted within a piston housing 25 to define a piston chamber 27. The apparatus 18 further comprises a rotary valve assembly 29 operated by relative rotation between the mandrel 20 and the bearing sleeve 24 to cyclically pressurise and depressurise the piston chamber 27 to provide reciprocating movement of the reciprocating piston 23 and the generation of vibration within the apparatus 18.

Abstract: A reciprocating drive apparatus (10) comprises a housing (12) and a mandrel (14), wherein the mandrel (14) and the housing (12) are configurable to be rotated relative to each other. The apparatus (10) further comprises a reciprocating piston (16) mounted within a piston housing (18) to define a piston chamber (20a), wherein the piston (16) is moveable in reverse first and second axial directions (A,B), and a rotary valve assembly (24) comprising a valve inlet (28) for communicating with a pressure region (P) and a valve exhaust (30) for communicating with an exhaust region (E). The rotary valve assembly (24) is operated by relative rotation between the mandrel (14) and the housing (12) to be cyclically reconfigured between a pressure configuration and an exhaust configuration.

Abstract: A swivel (100) is described comprising a first swivel member (112) comprising a first load shoulder (116) and a second swivel member (115) comprising a second load shoulder (118). The first and second swivel members are rotatable relative to each other. A deformable bearing component (142) is provided within a cavity (140) defined between the first and second load shoulder (116, 118). The deformable bearing component (142) facilitates load transmission between the first and second load shoulders (116, 118) and is deformable to accommodate variations in alignment between the first and second load shoulders (116, 118).

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions, and memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. The memory access circuitry determines, according to a programmable mapping, a mapping of guard tag storage locations for storing guard tags for corresponding blocks of memory locations.

Abstract: A thrust bearing is described comprising first and second bearing assemblies (15, 17) rotatable relative to each and a plurality of axially arranged bearing stages (14a, 14b) formed between the first and second bearing assemblies (15, 17). Each bearing stage comprises a first load shoulder (16) provided on the first bearing assembly (15), a second load shoulder (18) provided on the second bearing assembly (17), a bearing structure (30) defined between the first and second load shoulders; and an extrudable component (32) forming part of the bearing structure. Wherein axial load applied between the first and second bearing assemblies (15, 17) in a first relative axial direction is transmitted between respective pairs of first and second load shoulders via the extrudable components (32) of respective bearing structures (30). The extrudable components (30) provide for load balancing between each bearing stage (14a, 14b).

Abstract: An apparatus comprises address translation circuitry (70) to perform a translation of a virtual address (80) comprising a virtual tag portion (88) and a virtual address portion (86) into a physical address (82) comprising a physical tag portion (92) and a physical address portion (90). The address translation circuitry comprises address tag translation circuitry (72) to perform a translation of the virtual tag portion into the physical tag portion and the address translation to be performed is selected in dependence on the virtual address.

Abstract: An apparatus has processing circuitry (4); memory access circuitry (15) to perform a guard tag check for a tag checking target address having an associated address tag, the guard tag check comprising comparing the address tag with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and an instruction decoder (6) responsive to a random tag setting instruction specifying a tag setting target address, to control the processing circuitry (4) to set the address tag associated with the tag setting target address to a random tag value randomly selected from a set of candidate tag values.

Abstract: An apparatus comprising memory access circuitry to perform a tag-guarded memory access in response to a received target address and methods of operation of the same are disclosed. In the tag-guarded memory access a guard-tag retrieval operation seeks to retrieve a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the received target address, and a guard-tag check operation compares an address tag associated with the received target address with the guard tag retrieved by the guard-tag retrieval operation. When the guard-tag retrieval operation is unsuccessful in retrieving the guard tag, a substitute guard tag value is stored as the guard tag in association with the block of one or more memory locations comprising the addressed location identified by the target address.

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks.

Abstract: An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.

Abstract: An apparatus and method are provided for managing use of capabilities. The apparatus has processing circuitry to execute instructions, and a plurality of capability storage elements accessible to the processing circuitry and arranged to store capabilities used to constrain operations performed by the processing circuitry when executing instructions. The processing circuitry is operable at a plurality of exception levels, each exception level having different software execution privilege. Further, capability configuration storage is provided to identify capability configuration information for each of the plurality of exception levels. For each exception level, the capability configuration information identifies at least whether the operations performed by the processing circuitry when executing instructions at that exception level are constrained by capabilities.

Abstract: A jarring apparatus includes first and second jarring assemblies which are axially moveable relative to each other between first and second axial configurations, and a thrust assembly interposed between the first and second jarring assemblies to limit relative axial movement therebetween at the second axial configuration and permit axial loading in one axial direction to be transferred between the first and second jarring assemblies via the thrust assembly. The apparatus further includes a jarring mass axially moveable within the jarring apparatus in reverse first and second directions upon relative rotation between the first and second jarring assemblies.

Abstract: An apparatus comprises memory access circuitry to perform a tag-guarded memory access in response to a target address, the tag-guarded memory access comprising a guard-tag check of comparing an address tag associated with the target address with a guard tag stored in association with a block of one or more memory locations comprising an addressed location identified by the target address. The memory access circuitry is responsive to a sequence of received target addresses specifying a sequence of addressed locations to perform a non-tag-guarded memory access that does not perform the guard-tag check to a subset of the sequence of addressed locations.

Abstract: An apparatus and method are provided for managing a capability domain. The apparatus has processing circuitry for executing instructions, the processing circuitry when in a default state being arranged to operate in a capability domain comprising capabilities used to constrain operations performed by the processing circuitry when executing the instructions. A program counter capability storage element is also provided to store a program counter capability used by the processing circuitry to determine a program counter value. The program counter capability is arranged to identify a capability state for the processing circuitry. The processing circuitry is then arranged, when the capability state indicates the default state, to operate in the capability domain. However, when the capability state indicates the executive state, the processing circuitry is arranged to operate in a manner less constrained than when in the default state so as to allow modification of the capability domain.

Abstract: An apparatus has memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. An instruction decoder decodes a multiple guard tag setting instruction to control the memory access circuitry to trigger memory accesses to update the guard tags associated with at least two consecutive blocks of one or more memory locations.

Abstract: An apparatus (2) comprises an instruction decoder (6) and processing circuitry (4). The instruction decoder (6) supports branch instructions for triggering a non-sequential change of program flow to an instruction at a target address, including: a branch-with-link instruction for which a return address is set for a subsequent return of program flow; and at least one target-checking type of branch instruction, for which when the branch is taken an error handling response is triggered when the instruction at the target address is an instruction other than at least one permitted type of branch target instruction. For at least a subset of the at least one target-checking type of branch instruction, a branch target variant of the branch-with-link instruction is a permitted type of branch target instruction.

Abstract: A valve apparatus, such as a downhole valve apparatus, includes a housing having a flow path therein and a valve member mounted within the housing and being operable between closed and open configurations to control flow along the flow path. An actuator assembly is moveable from a first position to a second position to sequentially perform first and second actuation functions, the first actuation function being associated with the operation of an auxiliary system, and the second actuation function opening the valve member from its closed configuration.

Abstract: A data processing apparatus 2 includes a cache memory 8 for storing data items to be accessed. Coherency control circuitry 20 controls coherency between data items stored within the cache memory and one or more other copies of the data items stored outside the cache memory. A data access buffer 6 buffers a plurality of data access to respective data items stored within the cache memory. Access control circuitry 20 is responsive to coherency statuses managed by the coherency control circuitry for the plurality of data items to be subject to data access operations to be performed together atomically as an atomic set of data accesses to ensure that the coherency statuses for all of these data items permit all of the atomic set of data accesses to be performed within the cache memory before the set of atomic data accesses are commenced.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions, and memory access circuitry to perform a tag-guarded memory access operation in response to a target address. The tag-guarded memory access operation comprises comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address, and generating an indication of whether a match is detected between the guard tag and the address tag. The memory access circuitry determines, according to a programmable mapping, a mapping of guard tag storage locations for storing guard tags for corresponding blocks of memory locations.