Patents by Inventor Peter Barry

Peter Barry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240103143
    Abstract: False radar target detection incudes: generating a pair of entangled photons as a probe photons and idler photons; preparing a plurality of photon states; using the ancilla photon states to encode the probe photons and the idler photons; encoding the probe photons and the idler photons with the ancilla photon states; storing the idler photons; transmitting the probe and ancilla photons as a radar signal; receiving a return radar signal from the target; performing a quantum error detection on the return radar signal to determine whether there is an error in the received radar signal as a result of decoherence in the return signal; and correlating the probe signal, the idler states and analyzing the errors detected on the return radar signal to determine whether the target is a true target when there is low decoherence in the return radar signal.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 28, 2024
    Inventors: Sebastian Chiaramida, Peter Barry Morris
  • Patent number: 11912615
    Abstract: Glass-based articles comprise stress profiles providing improved fracture resistance. The glass-based articles herein provide high fracture resistance after multiple drops.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: February 27, 2024
    Assignee: CORNING INCORPORATED
    Inventors: Timothy Michael Gross, Xiaoju Guo, Jason Thomas Harris, Peter Joseph Lezzi, Alexandra Lai Ching Kao Andrews Mitchell, Pascale Oram, Kevin Barry Reiman, Rostislav Vatchev Roussev, Ljerka Ukrainczyk
  • Patent number: 11900152
    Abstract: Systems and methods are described for providing updating of disk images supporting serverless code execution and controlled deployment of updated disk images. A disk image can be defined as a set of layers that represent a file system include code of a serverless function and other data used by the code. A function owner can designate one layer as containing software or other data subject to update. When a new version of the layer is obtained at a serverless compute system, the system can generate a new disk image containing the updated layer. The system can then gradually transition the function to the new disk image, by dividing calls to the function among two versions of the function—one using the prior disk image, and one using the new disk image. Performance data gained from the new version of the function can be used to control the gradual transition.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Amazon Technologies, Inc.
    Inventors: Marc Brooker, David Nasi, Trishika Pattabiraman, Holly Mesrobian, Mikhail Danilov, Peter Barry, Peter Martin McDonnell
  • Publication number: 20240011047
    Abstract: In one aspect, the present invention provides recombinant polynucleotides. In some embodiments, the recombinant polynucleotides comprise a cytomegalovirus (CMV) genome, or a portion thereof, and a nucleic acid sequence encoding an antigen, wherein the CMV genome or portion thereof comprises a mutation within a interleukin-10-like gene sequence. Methods for preventing and treating diseases such as infectious diseases and cancer are also provided herein.
    Type: Application
    Filed: December 12, 2022
    Publication date: January 11, 2024
    Applicants: The Regents of the University of California, The UAB Research Foundation
    Inventors: Peter Barry, Dennis Hartigan-O'Connor, Ellen Sparger, William Chang, Mark Walter, Corey Miller
  • Publication number: 20230399797
    Abstract: An insulating rope includes: a non-conductive core; an extruded thermoplastic jacket disposed around the core; and a water adsorbent material disposed between the jacket and the core. A method of making an insulating rope is also described.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 14, 2023
    Applicant: BARRY CORDAGE LTD.
    Inventors: PETER BARRY, PATRICK BARRY
  • Patent number: 11755496
    Abstract: A computer system and methods are disclosed for mitigating side-channel attacks using memory aliasing. The computer system includes a memory, a memory controller and a cache. Responsive to determining to share a memory location among processes, the address of the memory may be aliased to another address within the same address space, with the address and aliased address assigned to respective ones of the processes. The memory controller manages the address space according to an aliasing region and a non-aliasing region, with addresses corresponding to the non-aliasing region being passed through to the memory. Addresses corresponding to the aliasing region are translated by the memory controller to match corresponding non-aliased memory addresses allowing aliased and non-aliased addresses to access same memory locations. A cache may cache accesses to memory addresses, including the non-aliased and aliased addresses, with different cache locations for selected according to the respective addresses of memory.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 12, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Peter Barry, Adi Habusha, Martin Pohlack
  • Patent number: 11635919
    Abstract: A computing device including executable processes may determine that a future likelihood of access for virtual memory pages of an executable process are below a threshold likelihood of access based on an execution status of the executable process or a tracking of memory accesses to the virtual memory pages of the executable process. Responsive to this determination, memory pages found to store contents matching that of memory pages mapped to other processes may be unmapped from the process and released for reuse by the computing device. The virtual memory pages may then be marked as being shared with the similar memory pages mapped to the other processes. At a later time, the memory pages of the process may be configured to be non-shared, the configuring including either copying respective shared pages to non-shared pages or enabling a processor exception on access to the memory pages.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 25, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Martin Pohlack, Peter Barry, Filippo Sironi
  • Publication number: 20220179636
    Abstract: The present disclosure relates to a verification controller for a vehicle, configured to receive data being sent over a data bus within the vehicle, detect software update data being sent to a control unit within the vehicle over the data bus, determine from the software update data a first security characteristic associated with an authentic version of the software update, generate a second security characteristic in dependence on the received software update data, determine if the second security characteristic is consistent with the first security characteristic, and output a first control signal for the control unit, the first control signal enabling installation of the software update on the control unit in dependence on the second security characteristic being consistent with the first security characteristic.
    Type: Application
    Filed: March 6, 2020
    Publication date: June 9, 2022
    Inventors: Peter BARRY, Javier OLARRETA
  • Publication number: 20220105173
    Abstract: The present invention provides compositions and methods for inducing immune responses in subjects using HV-based vectors that can be grown in single celled organisms and administered in their nucleic acid form.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 7, 2022
    Applicant: The Regents of the University of California
    Inventors: Dennis Hartigan-O'Connor, Peter Barry, Jesse Deere, Joseph Dutra
  • Publication number: 20210123074
    Abstract: In one aspect, the present invention provides recombinant polynucleotides. In some embodiments, the recombinant polynucleotides comprise a cytomegalovirus (CMV) genome, or a portion thereof, and a nucleic acid sequence encoding an antigen, wherein the CMV genome or portion thereof comprises a mutation within a interleukin-10-like gene sequence. Methods for preventing and treating diseases such as infectious diseases and cancer are also provided herein.
    Type: Application
    Filed: September 4, 2020
    Publication date: April 29, 2021
    Applicants: The Regents of the University of California, The UAB Research Foundation
    Inventors: Peter Barry, Dennis Hartigan-O'Connor, Ellen Sparger, William Chang, Mark Walter, Corey Miller
  • Patent number: 10876125
    Abstract: There is provided a non-PCR based method for construction of a DNA recombination fragment with necessary flanking regions homologous to a desired site of genetic manipulation within a target DNA required for recombination-based manipulation of said target DNA, comprising the steps of: A) identifying a desired site of insertion for a genetic element in said target DNA; B) locating an endogenous, native, half-site of a selected restriction endonuclease present upstream of the site within the DNA to be targeted for genetic manipulation and thereby defining the 5? extent of an upstream homology region; C) locating an endogenous, native, half-site of the same selected restriction endonuclease present downstream of the site within the DNA to be targeted for genetic manipulation and thereby defining the 3? extent of a downstream homology region; D) synthesising a flanking region cassette resulting in juxtapositioning of the upstream and downstream half-sites thereby causing formation of complete restriction site for
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 29, 2020
    Assignees: UNIVERSITY OF PLYMOUTH, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Michael Jarvis, Aisling Murphy, Peter Barry
  • Patent number: 10472605
    Abstract: A serum-free medium for the growth of mesenchymal stem cells comprises FGF, TGF-? and lipoprotein.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: November 12, 2019
    Assignee: National University of Ireland, Galway
    Inventors: Francis Peter Barry, Emma Jane Mooney, Josephine Mary Murphy, Georgina Margaret Shaw, Sean Patrick Gaynard
  • Publication number: 20180237788
    Abstract: There is provided a non-PCR based method for construction of a DNA recombination fragment with necessary flanking regions homologous to a desired site of genetic manipulation within a target DNA required for recombination-based manipulation of said target DNA, comprising the steps of: A) identifying a desired site of insertion for a genetic element in said target DNA; B) locating an endogenous, native, half-site of a selected restriction endonuclease present upstream of the site within the DNA to be targeted for genetic manipulation and thereby defining the 5? extent of an upstream homology region; C) locating an endogenous, native, half-site of the same selected restriction endonuclease present downstream of the site within the DNA to be targeted for genetic manipulation and thereby defining the 3? extent of a downstream homology region; D) synthesising a flanking region cassette resulting in juxtapositioning of the upstream and downstream half-sites thereby causing formation of complete restriction site for
    Type: Application
    Filed: August 5, 2016
    Publication date: August 23, 2018
    Applicants: University of Plymouth, The Regents of the University of California
    Inventors: Michael JARVIS, Aisling MURPHY, Peter BARRY
  • Publication number: 20170044489
    Abstract: A serum-free medium for the growth of mesenchymal stem cells comprises FGF, TGF-? and lipoprotein.
    Type: Application
    Filed: February 16, 2015
    Publication date: February 16, 2017
    Applicant: National University of Ireland, Galway
    Inventors: Francis Peter BARRY, Emma Jane MOONEY, Josephine Mary MURPHY, Georgina Margaret SHAW, Sean Patrick GAYNARD
  • Publication number: 20170044497
    Abstract: A population of human stem cells is, or is selected to be, positive for CD271 and acetylated tubulin. Cells are isolated by a method comprising isolation of a cell from a mixed population of cells based on expression of cell surface markers, wherein the markers are CD271 and acetylated tubulin. The isolated cells may be used in therapy for example by producing tissues such as bone, cartilage or tendon, or in pharmaceutical compositions comprising isolated cells.
    Type: Application
    Filed: February 12, 2015
    Publication date: February 16, 2017
    Applicant: National University of Ireland, Galway
    Inventors: Francis Peter BARRY, Aline Myriam MORRISON
  • Patent number: 9535838
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: January 3, 2017
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 9442855
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Patent number: 9321813
    Abstract: The present invention provides methods and compositions for treating and/or preventing a cytomegalovirus infection in a subject, comprising administering to the subject an effective amount of a cytomegalovirus interleukin-10 (IL-10) protein modified to have reduced functional activity while retaining immunogenicity. The present invention further provides nucleic acid molecules encoding a cytomegalovirus IL-10 protein or fragment thereof of this invention as well as vectors comprising such nucleic acids. Also provided herein are neutralizing antibodies that specifically bind cmvIL-10.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: April 26, 2016
    Assignees: UAB Research Foundation, The Regents of the University of California
    Inventors: Mark R. Walter, Peter A. Barry
  • Patent number: 9098415
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia
  • Publication number: 20150161050
    Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 11, 2015
    Inventors: Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David J. Harriman, Mark B. Rosenbluth, Ajay V. Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert G. Blankenship, Ohad Falik, Avi Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia