Abstract: A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.

Abstract: A ramp buffer circuit includes a ramp buffer input device having an input coupled to receive a ramp signal. A current monitor is circuit coupled to a power line and the ramp buffer input device to generate a current monitor signal in response to an input current conducted through the ramp buffer input device. A corner bias circuit is coupled to the current monitor circuit to generate an assist bias voltage in response to the current monitor signal. A bias current source is coupled to an output of the ramp buffer input device. An assist current source is coupled to the corner bias circuit and coupled between the output of the ramp buffer input device and ground to conduct an assist current from the output of the ramp buffer input device to ground in response to the assist bias voltage.

Abstract: A power distribution network is disclosed. The power distribution can be applied to imaging arrays and other circuits that include a large number of conductors that must be driven such that the conductors are biased such that substantially the same current flows in each conductor. The power distribution network includes a plurality of bit lines and a first power connection network. Each bit line is connected to a different location on a first power bus, which is divided into a plurality of first conducting segments. Each first conducting segment is connected to a plurality of the bit lines. Each bit line includes a constant current source that causes a bias current to flow in the bit line and through the first power bus. The first power connection network includes a plurality of conducting paths that connect a corresponding one of the first conducting segments to a first power rail.

Abstract: An imaging sensor using a novel bit line processing circuit, that circuit, and the method of processing the pixel outputs from an image sensor using that processing circuit are disclosed. The image sensor includes an array of pixel sensors, a signal digitizing circuit, and a digitizing controller. Each pixel sensor generates a voltage signal that is a function of a charge on the photodetector in that pixel sensor, and couples that voltage signal to a bit line in response to a first signal. The signal digitizing circuit is connected to the bit line, the digitizing circuit converting the voltage signal to a plurality of output digital values, the output digital values having selectable levels of digitization noise. The digitizing controller generates the level of noise based on the voltage signal. The signal digitizing circuit includes a variable gain amplifier and an ADC having a fixed number of bits.

Abstract: An imaging sensor using a novel bit line processing circuit, that circuit, and the method of processing the pixel outputs from an image sensor using that processing circuit are disclosed. The image sensor includes an array of pixel sensors, a signal digitizing circuit, and a digitizing controller. Each pixel sensor generates a voltage signal that is a function of a charge on the photodetector in that pixel sensor, and couples that voltage signal to a bit line in response to a first signal. The signal digitizing circuit is connected to the bit line, the digitizing circuit converting the voltage signal to a plurality of output digital values, the output digital values having selectable levels of digitization noise. The digitizing controller generates the level of noise based on the voltage signal. The signal digitizing circuit includes a variable gain amplifier and an ADC having a fixed number of bits.

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract: A sample and hold circuit and a method for sampling a signal are disclosed. The sample and hold circuit includes first and second switches, first, second, and third capacitors, and an amplifier. The amplifier receives a signal to be sampled on a first input. The first capacitor is characterized by a first capacitance and has a first terminal connected to an output of the amplifier by the first switch. The second capacitor is characterized by a second capacitance and has a second terminal connected to the output of the amplifier by the second switch. The third capacitor connects the first and second terminals. The amplifier is configured to form a capacitive transimpedance amplifier having the third capacitor as a feedback circuit when the first switch is in a non-conducting state and the second switch is in a conducting state.

Abstract: An imaging system provides a serial video signal that is indicative of the intensity of the light. The imaging system has an array of pixel image sensors arranged in rows and columns. A control circuit is in communication with the rows of the array and the plurality of column switches. The control circuit generates reset control signals, transfer gating signals, pixel image sensor initiation signals for each selected row for controlling resetting, integration of photoelectrons generated from the light impinging upon the array of pixel image sensors, charge transfer of the photoelectrons from the photosensing devices to the charge storage device, and to activate the photoelectron sensing devices on each row to generate output signals from each of the pixel image sensors on a selected row. The control circuit generates the column selection signals for transfer of the output signals from selected rows to form a serial video output signal.

Abstract: An imaging system provides a serial video signal that is indicative of the intensity of the light. The imaging system has an array of pixel image sensors arranged in rows and columns. A control circuit is in communication with the rows of the array and the plurality of column switches. The control circuit generates reset control signals, transfer gating signals, pixel image sensor initiation signals for each selected row for controlling resetting, integration of photoelectrons generated from the light impinging upon the array of pixel image sensors, charge transfer of the photoelectrons from the photosensing devices to the charge storage device, and to activate the photoelectron sensing devices on each row to generate output signals from each of the pixel image sensors on a selected row. The control circuit generates the column selection signals for transfer of the output signals from selected rows to form a serial video output signal.

Abstract: An imaging system provides a serial video signal that is indicative of the intensity of the light. The imaging system has an array of pixel image sensors arranged in rows and columns. A control circuit is in communication with the rows of the array and the plurality of column switches. The control circuit generates reset control signals, transfer gating signals, pixel image sensor initiation signals for each selected row for controlling resetting, integration of photoelectrons generated from the light impinging upon the array of pixel image sensors, charge transfer of the photoelectrons from the photosensing devices to the charge storage device, and to activate the photoelectron sensing devices on each row to generate output signals from each of the pixel image sensors on a selected row. The control circuit generates the column selection signals for transfer of the output signals from selected rows to form a serial video output signal.

Abstract: An imaging system provides a serial video signal that is indicative of the intensity of the light. The imaging system has an array of pixel image sensors arranged in rows and columns. A control circuit is in communication with the rows of the array and the plurality of column switches. The control circuit generates reset control signals, transfer gating signals, pixel image sensor initiation signals for each selected row for controlling resetting, integration of photoelectrons generated from the light impinging upon the array of pixel image sensors, charge transfer of the photoelectrons from the photosensing devices to the charge storage device, and to activate the photoelectron sensing devices on each row to generate output signals from each of the pixel image sensors on a selected row. The control circuit generates the column selection signals for transfer of the output signals from selected rows to form a serial video output signal.