Abstract: A method of designing an integrated circuit including at least one predefined core module and a custom logic circuit whereby clock skew between the core module and the custom logic circuit may be reduced. An integrated circuit designer selects core modules having desired functionality for inclusion within an integrated circuit from a library of core modules. Each core module in the library is predefined and pre-verified and may be provided as a synthesizeable register-transfer level (RTL) description which can be synthesized along with RTL descriptions of other logic blocks in the integrated circuit. Alternatively, each core module may be provided as a pre-laidout integrated circuit mask which can be included in the final integrated circuit mask design. Upon selection of appropriate core modules, the designer defines a custom logic circuit for integration with the core modules.