Abstract: A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor structure is provided which comprises an active semiconductor layer (224) disposed on a buried dielectric layer (222). A trench (229) is created in the semiconductor structure which exposes a portion of the buried dielectric layer. An oxide layer (250) is formed over the surfaces of the trench, and at least one stressor structure (254) is formed over the oxide layer.

Abstract: A process of forming an electronic device can include patterning a semiconductor layer to define an opening. After patterning the semiconductor layer, the opening can have a bottom, and the semiconductor layer can have a sidewall and a surface. The surface is spaced apart from the bottom of the opening. The sidewall can extend from the surface towards the bottom of the opening. The process can also include forming a layer over the semiconductor layer and within the opening, and removing a part of the first layer from within the opening. After removing the part of the layer, a remaining portion of the layer may lie within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the layer may be spaced apart from the surface. In another aspect, the electronic device can include a field isolation region including the first layer.

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (225) having a more uniform polish surface (300) by thickening an SOI semiconductor layer (210) in relation to a previously or subsequently formed epitaxial silicon layer (220) with a selective silicon deposition process that covers the SOI semiconductor layer (210) with a crystalline semiconductor layer (216). By forming first gate electrodes (151) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (16) by selectively depositing an epitaxial silicon layer (70) to fill a trench (96), and then blanket depositing silicon to cover the entire wafer with near uniform thickness of crystalline silicon (102) over the epi silicon layer (70) and polycrystalline silicon (101, 103) over the nitride mask layer (95). The polysilicon material (101, 103) added by the two-step process increases the polish rate of subsequent CMP polishing to provide a more uniform polish surface (100) over the entire wafer surface, regardless of variations in structure widths and device densities. By forming first gate electrodes (151) over a first SOI layer (90) using deposited (100) silicon and forming second gate electrodes (161) over an epitaxially grown (110) silicon layer (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.

Abstract: A structure in a semiconductor device useful in determining an endpoint in a chemical-mechanical polishing process is provided. The structure comprises a dielectric layer, an anti-reflective coating, and a metal layer. The dielectric layer has an opening extending therein. The anti-reflective coating extends over at least a portion of the first dielectric layer. The metal layer extends over at least a portion of the anti-reflective coating and within the opening. Thus, during the CMP process, the metal layer is removed, exposing the anti-reflective coating but leaving the metal layer in the opening to form a metal interconnect.

Abstract: Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during manufacturing. For example, densification heating may be done at a temperature of at least 1100 degrees Celsius for at least 10 minutes after filling the isolation trenches (22, 24) with dielectric material (30). This densification heating may improve the variation in threshold voltages of transistors (e.g. 48) on an integrated circuit (49), particularly SOI (silicon on insulator) devices. SRAM cells (50) in particular may benefit from this densification heating.