Abstract: The invention relates to a system and a method for automated transfer and subsequent evaluation of the quality of mass data of a technical process or a technical project in a standardized environment (70) of one or more data processing devices with an assignment module (20) for allocating the mass data from one or more data sources (10) to structure elements in the standardized environment of the data processing device (70) and for generating a defined mapping of the mass data to be read in. The assignment module (20) interacts with a read-in module (30), into which the mass data can be read in an automated operation according to the selected assignment. The data read in can be fed to a checking module (40) for automated checking and/or for generation of a report for evaluation of the quality of the measured data read in.

Abstract: In an embodiment, an integrated semiconductor memory includes a plurality of data lines via which data read out or to be read out from memory cells can be communicated, wherein the data lines comprise redundant data lines and non-redundant data lines, wherein the semiconductor memory has at least one data distributor line, and wherein a plurality of redundant data lines are connected up to the at least one data distributor line in such a way that in each case a redundant data line or a group of redundant data lines from the plurality of redundant data lines can be selected and can be connected to the at least one data distributor line.

Abstract: A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch.

Abstract: According to one embodiment of the present invention, a method of operating an integrated circuit including a plurality of resistivity changing memory cells connected in parallel is provided. The method includes: choosing a resistivity changing memory cell having a first memory state out of the plurality of resistivity changing memory cells; measuring a first total resistance of the plurality of resistivity changing memory cells; setting the chosen resistivity changing memory cell to a second memory state, measuring a second total resistance of the plurality of resistivity changing memory cells; and determining the first memory state of the chosen resistivity changing memory cell in dependence on the first total resistance and the second total resistance.

Abstract: An integrated electrical module has a set of regular elements and a set of redundant elements, the elements being split over at least two blocks which are individually selectable by an input address and respectively containing regular elements and redundant elements. The integrated electrical module further has two repair circuits, each repair circuit being associated to a block, the two repair circuits being conditioned as a pair for a partner mode of operation, in which the addressing of an element from a first half-group of regular elements in the first block is diverted to a first half-group of elements in the second block and the addressing of an element from a second half-group of regular elements in the first block is diverted to a second half-group of elements in the second block.

Abstract: A memory device comprising a memory cell and an evaluation circuit, the memory cell being coupled with the evaluation circuit via a bit line. The memory device further comprises a reference line coupled with the evaluation circuit, the evaluation circuit being designed for amplifying a difference between electric potentials of the bit line and the reference line. Inputs of the evaluation circuit are directly connected to the bit line. Outputs of the evaluation circuit are coupled to the bit line via a switch.

Abstract: Embodiments of the present invention generally provide methods and apparatus for testing memory devices having normal memory elements and redundant memory elements. During a front-end testing procedure, normal memory elements that are found to be defective are replaced by redundant memory elements. During the front-end test, redundant memory elements that are found to be defective may be marked as defective by blowing associated mask fuses. During a back-end testing procedure, the results of testing a normal memory element may be masked (e.g., forced to a passing result) if the normal memory element has been replaced by a redundant memory element. Similarly, the results of testing a redundant memory element may be masked if the redundant memory element was previously found to be defective, as indicated by an associated mark fuse.

Abstract: Method and apparatus for accessing a memory, wherein the memory has a cell array having a number of memory cells arranged in cell array elements. A cell array element determined to be defective is deactivate. After the cell array element is deactivated, an address of a cell array element is applied to an activation apparatus of the memory in order to activate the cell array element for a given memory access. The applied address is compared with stored error addresses which are assigned to defective cell array elements. In the event of a match between the applied address and one of the error addresses, a redundant cell array element is activated instead of the cell array element.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: The invention relates to a system and a method for automated transfer and subsequent evaluation of the quality of mass data of a technical process or a technical project in a standardized environment (70) of one or more data processing devices with an assignment module (20) for allocating the mass data from one or more data sources (10) to structure elements in the standardized environment of the data processing device (70) and for generating a defined mapping of the mass data to be read in. The assignment module (20) interacts with a read-in module (30), into which the mass data can be read in an automated operation according to the selected assignment. The data read in can be fed to a checking module (40) for automated checking and/or for generation of a report for evaluation of the quality of the measured data read in.

Abstract: In an embodiment, an integrated semiconductor memory includes a plurality of data lines via which data read out or to be read out from memory cells can be communicated, wherein the data lines comprise redundant data lines and non-redundant data lines, wherein the semiconductor memory has at least one data distributor line, and wherein a plurality of redundant data lines are connected up to the at least one data distributor line in such a way that in each case a redundant data line or a group of redundant data lines from the plurality of redundant data lines can be selected and can be connected to the at least one data distributor line.

Abstract: Method and apparatus for accessing a memory, wherein the memory has a cell array having a number of memory cells arranged in cell array elements. A cell array element determined to be defective is deactivate. After the cell array element is deactivated, an address of a cell array element is applied to an activation apparatus of the memory in order to activate the cell array element for a given memory access. The applied address is compared with stored error addresses which are assigned to defective cell array elements. In the event of a match between the applied address and one of the error addresses, a redundant cell array element is activated instead of the cell array element.

Abstract: A system and a method are disclosed for automated quantity-related comparison between planning/project and default data of a technical process or a technical project, with an input module for the supply of the default data and a planning tool for storage of the planning data. The input module is provided to transmit the individual elements of the default data as default elements to the planning tool for further processing. The planning tool has a planning module, in which the individual elements of the planning data are stored as planning elements. The planning tool further has an assignment module for generating a mapping of the default elements on to the planning elements. Based on the generated mapping of the default elements on to the planning elements, a processing module integrated in the planning tool automatically performs a quantity-related comparison between the number of planning elements and of default elements, and makes the comparison results available to an evaluation module.

Abstract: An integrated electrical module has a set of regular elements and a set of redundant elements, the elements being split over at least two blocks which are individually selectable by an input address and respectively containing regular elements and redundant elements. The integrated electrical module further has two repair circuits, each repair circuit being associated to a block, the two repair circuits being conditioned as a pair for a partner mode of operation, in which the addressing of an element from a first half-group of regular elements in the first block is diverted to a first half-group of elements in the second block and the addressing of an element from a second half-group of regular elements in the first block is diverted to a second half-group of elements in the second block.

Abstract: A system and a method are disclosed for the automated and structured transfer of technical documents and the management of the transferred documents in a database of an engineering process or an engineering project with at least one data source, in which the documents are stored in electronic form. One or more structures for storing the documents are implemented in the database. The structures are identifiable by means of an assigned identification feature. The data source interacts with an assignment module, which allocates each document a document identification number for unique assignment into one of the structures of the database. The data source further interacts with a sort module, which files the documents dependent on their document identification number in the structure identifiable by the identification feature in the database, and makes the documents available for further processing.

Abstract: An integrated memory having a plurality of memory banks includes a test circuit for functional testing of the memory. A plurality of secondary sense amplifiers are assigned to a different one of the memory banks. The test circuit includes a data generator for generating read comparison data. A plurality of comparison circuits are assigned to a different one of the memory banks to compare test data read from the assigned memory bank with the read comparison data. A first input of the respective comparison circuit can be connected to the secondary sense amplifier without interposition of the read/write data lines. A second input can be connected to the read/write data lines to receive the read comparison data supplied by the data generator. An output signal of the respective comparison circuit depends on the comparison result of a data comparison of the first and second inputs.

Abstract: The invention relates to an integrated memory module having a memory unit and a self-test circuit, the self-test circuit being embodied in such a way as to make available test data and test addresses for testing memory areas in the memory unit and to generate defect data depending on the detection of a defect, a test circuit being provided in order to receive defect data from one or a plurality of connectable memory modules to be detected, the test circuit being configured in such a way as to store the received defect data depending on addresses assigned thereto in the memory unit.

Abstract: A magnetoresistive memory element includes a stacked structure with a ferromagnetic reference region including a fixed magnetization; a ferromagnetic free region including a free magnetization that is free to be switched between oppositely aligned directions with respect to an easy axis thereof; and a tunneling barrier made of a non-magnetic material. The ferromagnetic reference and free regions and the tunneling barrier together form a magnetoresistive tunneling junction. The ferromagnetic free region includes a plurality of N ferromagnetic free layers being magnetically coupled such that magnetizations of adjacent ferromagnetic free layers are in antiparallel alignment, where N is an integer greater than or equal to two. The ferromagnetic free region further includes at least one ferromagnetic decoupling layer including frustrated magnetization in orthogonal alignment to ferromagnetic free layer magnetizations and being arranged in between adjacent ferromagnetic free layers.

Abstract: A test circuit for testing a memory circuit has a data input line for providing test data and a comparator unit. The comparator unit is connected to the data input line and to the memory circuit for comparing the test data written into the memory circuit with the test data read from the memory area. The data input line is connected to the memory circuit via a data change circuit. The data change circuit is controllable depending on a result of a comparison in the comparator unit such that when an error occurs, subsequent test data can be written in an altered manner to the memory circuit.

Abstract: A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.