Patents by Inventor Peter Beerel
Peter Beerel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9875327Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.Type: GrantFiled: February 4, 2016Date of Patent: January 23, 2018Assignee: University of Southern CaliforniaInventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
-
Patent number: 9558309Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.Type: GrantFiled: May 1, 2015Date of Patent: January 31, 2017Assignee: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
-
Publication number: 20160154905Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.Type: ApplicationFiled: February 4, 2016Publication date: June 2, 2016Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
-
Publication number: 20150326210Abstract: An asynchronous circuit may include a single-rail logic datapath; one or more error-detecting latches; a controller that controls the error-detecting latches; and delay lines. The controller and the delay lines may cooperate to communicate with one or more other controllers that the output of the controlled error-detecting latches may be valid prior to when the error-detecting latches indicate whether or not an error occurred.Type: ApplicationFiled: May 1, 2015Publication date: November 12, 2015Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Peter A. Beerel, Melvin Breuer, Benmao Cheng, Dylan Hand
-
Patent number: 8972915Abstract: Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty™ file format, before being compatible with commercial STA tools.Type: GrantFiled: February 12, 2009Date of Patent: March 3, 2015Assignee: University of Southern CaliforniaInventors: Mallika Prakash, Peter A. Beerel
-
Patent number: 8495543Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.Type: GrantFiled: June 17, 2009Date of Patent: July 23, 2013Assignees: University of Southern California, Fulcrum Microsystems, Inc.Inventors: Georgios Dimou, Peter A. Beerel, Andrew Lines
-
Patent number: 8448105Abstract: Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.Type: GrantFiled: April 24, 2009Date of Patent: May 21, 2013Assignees: University of Southern California, Fulcrum Microsystems, Inc.Inventors: Georgios Dimou, Peter A. Beerel, Andrew Lines
-
Patent number: 8086975Abstract: Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.Type: GrantFiled: April 10, 2009Date of Patent: December 27, 2011Assignees: University of Southern California, Fulcrum Microsystems, Inc.Inventors: Ken Shiring, Peter A. Beerel, Andrew Lines, Arash Saifhashemi
-
Patent number: 8051396Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.Type: GrantFiled: May 4, 2009Date of Patent: November 1, 2011Assignee: Fulcrum Microsystems, Inc.Inventors: Peter Beerel, Andrew Lines, Michael Davies
-
Publication number: 20110029941Abstract: Techniques are described for generating asynchronous circuits (e.g., in the form of one or more netlists) for implementation, e.g., in integrated circuitry/chips. Embodiments are directed to asynchronous multi-level domino design template and several variants including a mixture of domino and single-rail data logic. The templates can provide high throughput, low latency, and area efficiency. A multi-level domino template is partitioned into pipeline stages in which each stage consists of potentially multiple-levels of domino logic controlled by a single controller that communicates with other controllers via handshaking. Each stage is composed of two parts: a data path and a control path. The data path implements the computational logic, both combinational and sequential using efficient dual-rail domino logic. The control path implements a unique four-phase handshake to ensure correctness and the preservation of logical dependencies between pipeline stages.Type: ApplicationFiled: June 17, 2009Publication date: February 3, 2011Applicants: UNIVERSITY OF SOUTHERN CALIFORNIA, FULCRUM MICROSYSTEMS, INC.Inventors: Georgios Dimou, Peter A. Beerel, Andrew Lines
-
Publication number: 20090288059Abstract: Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.Type: ApplicationFiled: April 24, 2009Publication date: November 19, 2009Applicants: UNIVERSITY OF SOUTHERN CALIFORNIA, FULCRUM MICROSYSTEMS, INC.Inventors: Georgios Dimou, Peter A. Beerel, Andrew Lines
-
Publication number: 20090288058Abstract: Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.Type: ApplicationFiled: April 10, 2009Publication date: November 19, 2009Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Ken Shiring, Peter A. Beerel, Andrew Lines, Arash Saifhashemi
-
Patent number: 7584449Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.Type: GrantFiled: November 10, 2005Date of Patent: September 1, 2009Assignee: Fulcrum Microsystems, Inc.Inventors: Peter Beerel, Andrew Lines, Michael Davies
-
Publication number: 20090217232Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.Type: ApplicationFiled: May 4, 2009Publication date: August 27, 2009Applicant: FULCRUM MICROSYSTEMS, INC.Inventors: Peter Beerel, Andrew Lines, Michael Davies
-
Publication number: 20090210841Abstract: Effective timing and power characterization flows are described for asynchronous circuits. Verification can be provided for both relative-timing constraints as well as performance (e.g., throughput) targets using commercially-standard STA tools. Fully-automated scripts are developed that verify all relative timing assumptions (e.g., isochronic forks) as well as the gate-level performance of any circuit designed with these templates. Library characterization can be utilized and asynchronous logic cells not found in standard-cell libraries, such as dual-rail domino logic and dynamic C-elements with staticizers, can be characterized in terms of both their timing and power. These values are a function of both input slew and output load and are preferably captured in an industry standard format, such as the Liberty format, before being compatible with commercial STA tools.Type: ApplicationFiled: February 12, 2009Publication date: August 20, 2009Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Mallika Prakash, Peter A. Beerel
-
Patent number: 7197691Abstract: Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.Type: GrantFiled: June 24, 2004Date of Patent: March 27, 2007Assignee: University of Southern CaliforniaInventors: Peter A. Beerel, Keith M. Chugg, Georgios D. Dimou, Phunsak Thiennviboon
-
Publication number: 20060120189Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.Type: ApplicationFiled: November 10, 2005Publication date: June 8, 2006Inventors: Peter Beerel, Andrew Lines, Michael Davies
-
Patent number: 6854096Abstract: Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.Type: GrantFiled: July 14, 2003Date of Patent: February 8, 2005Assignee: Fulcrum Microsystems, Inc.Inventors: Frederik Eaton, Peter Beerel
-
Publication number: 20040237025Abstract: Decoding an encoded signal (for example, a turbo encoded signal, a block encoded signal or the like) is performed by demodulating the received encoded signal to produce soft information, and iteratively processing the soft information with one or more soft-in/soft-output (SISO) modules. At least one of the SISO modules uses a tree structure to compute forward and backward state metrics. More generally, iterative detection is performed by receiving an input signal corresponding to one or more outputs of a module whose soft-inverse can be computed by running the forward-backward algorithm on a trellis representation of the module, and determining the soft inverse of the module by computing forward and backward state metrics of the received input signal using a tree structure.Type: ApplicationFiled: June 24, 2004Publication date: November 25, 2004Applicant: University of Southern CaliforniaInventors: Peter A. Beerel, Keith M. Chugg, Georgios D. Dimou, Phunsak Thiennviboon
-
Patent number: 6785875Abstract: Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.Type: GrantFiled: January 28, 2003Date of Patent: August 31, 2004Assignee: Fulcrum Microsystems, Inc.Inventors: Peter Beerel, Andrew Lines, Qing Wu