Patents by Inventor Peter Beerel

Peter Beerel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240205563
    Abstract: Provided is an integrated circuit comprising: a sensor structure; a set of weighting elements, each configured to weight an output of the sensor structure; and an output element, the output element configured to collect weighted outputs of the set of weighting elements.
    Type: Application
    Filed: December 19, 2023
    Publication date: June 20, 2024
    Inventors: Peter Beerel, Gourav Datta, Ajey P. Jacob, Akhilesh Jaiswal, Zihan Yin
  • Patent number: 8051396
    Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: November 1, 2011
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Peter Beerel, Andrew Lines, Michael Davies
  • Patent number: 7584449
    Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: September 1, 2009
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Peter Beerel, Andrew Lines, Michael Davies
  • Publication number: 20090217232
    Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
    Type: Application
    Filed: May 4, 2009
    Publication date: August 27, 2009
    Applicant: FULCRUM MICROSYSTEMS, INC.
    Inventors: Peter Beerel, Andrew Lines, Michael Davies
  • Publication number: 20060120189
    Abstract: Methods and apparatus are described for optimizing a circuit design. A gate level circuit description corresponding to the circuit design is generated. The gate level circuit description includes a plurality of pipelines across a plurality of levels. Using a linear programming technique, a minimal number of buffers is added to selected ones of the pipelines such that a performance constraint is satisfied.
    Type: Application
    Filed: November 10, 2005
    Publication date: June 8, 2006
    Inventors: Peter Beerel, Andrew Lines, Michael Davies
  • Patent number: 6854096
    Abstract: Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 8, 2005
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Frederik Eaton, Peter Beerel
  • Patent number: 6785875
    Abstract: Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: August 31, 2004
    Assignee: Fulcrum Microsystems, Inc.
    Inventors: Peter Beerel, Andrew Lines, Qing Wu
  • Publication number: 20040103377
    Abstract: Methods and apparatus are described for facilitating physical synthesis of a circuit design. The circuit design includes a plurality cell instances organized hierarchically. Each cell instance corresponds schematically to one of a plurality of cell types. Transistors in each of the cell instances is sized with reference to an objective function thereby resulting in a first plurality of cell subtypes for each cell type. Each cell subtype corresponding to a particular cell type differs from all other cell subtypes corresponding to the particular cell type by at least one transistor dimension. Selected ones of the subtypes for at least one of the cell types are merged thereby resulting in a second plurality of subtypes for the at least one of the cell types. The second plurality of subtypes being fewer than the first plurality of subtypes. The merging of the selected subtypes achieves a balance between the objective function and a cost associated with maintaining the selected subtypes distinct.
    Type: Application
    Filed: July 14, 2003
    Publication date: May 27, 2004
    Applicant: Fulcrum Microsystems, Inc.
    Inventors: Frederik Eaton, Peter Beerel
  • Publication number: 20040034844
    Abstract: Methods and apparatus are described for facilitating physical synthesis of an integrated circuit design. A set of paths between observable nodes in a netlist representing the circuit design is generated. Each path corresponds to a sequence of signal transitions. Transistors represented in the netlist are sized to attempt to meet a delay constraint for each path. The delay constraint corresponds to a unit delay times the number of signal transitions in the corresponding path. A plurality of individual delays of different durations are allocated among the transitions for at least one of the paths to meet the delay constraint. At least one of the individual delays exceeds the unit delay.
    Type: Application
    Filed: January 28, 2003
    Publication date: February 19, 2004
    Applicant: Fulcrum Microsystems, Inc.
    Inventors: Peter Beerel, Andrew Lines, Qing Wu