Abstract: In order to securely hold an upright photovoltaic (PV) module (2), an associated sufficiently strong module holder (6) is provided, which can stabilize one or more outer edges of the PV module (2) against wind loads and at the same time minimizes the susceptibility of the PV module (2) to shading by the associated module holder (6). The module holder (6) has a convex shape, allowing large maximum shading-free angles of incidence (23, 24) at the front and rear and simultaneously achieving the lowest possible respective lateral expansion of the module holder (6) in a direction transverse to an active surface (9) of the PV module (2), namely both at the front and rear. This makes it possible to obtain powerful PV systems (1), based on a support structure (3), which, using the present module holders (6), hold large-surface-area bifacial PV modules (2) upright and in a largely shading-free manner.

Abstract: Foundry skew models represent the variation in various manufacturing parameters for a given semiconductor manufacturing process. Typically, foundry skew models are generated by the foundries by taking measurements on large numbers of wafers. In many cases skew models are not available for a new process or are suspect because they are based on limited actual measurements. Methods and systems are provided for using principal components analysis to generate foundry skew models for new semiconductor manufacturing processes that have limited or no actual measurements available. In one embodiment, the method generally comprises: selecting an existing foundry skew model for an existing semiconductor manufacturing process; selecting typical model parameters for the existing foundry skew model; and performing principal component analysis on the typical model parameters.

Abstract: A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.