Abstract: A flip chip having a chip passivation layer disposed on a metalization layer. Terminal vias are formed in the passivation layer exposing a portion of the metalization layer and terminal metalization is disposed on the metalization layer at the terminal vias. A stress reducing layer is disposed on the chip passivation layer with underfill apertures formed in the stress reducing layer so as to expose selected portions of the chip passivation layer, thereby enhancing the adhesion of an underfill material to the flip chip.

Abstract: A component package having a substrate. The substrate has a component or chip section and a separate assembly section. An array of component pads are disposed on the component section and are adapted to be electrically connected to a component. An array of assembly contact pads are disposed on the assembly section and are adapted to be connected to a next level assembly, such as a printed circuit board. The component contact pads are electrically connected to the assembly contact pads by electrical conductors affixed to the substrate. At least a portion of the substrate between the component section and the assembly section is flexible. The assembly section of the substrate can be secured to a rigid carrier and a casing (or overmolded top) can be mounted to the rigid carrier so as to protect a component enclosed in the package.

Abstract: A multiple layer interconnect structure for a semiconductor chip includes a graded transition layer of tungsten and a Group VIII metal, such as palladium, platinum or nickel (Pd, Pt or Ni) which allows formation of a Group VIII metal interconnect on a conventional pad of Al or Al alloy. The graded transition layer is interfaced between a thin adhesion layer on the pad and the Group VIII metal interconnect, and is approximately 100% tungsten where it interfaces the adhesion layer and approximately 100% Group VIII metal where it interfaces the interconnect layer. The tungsten in the graded transition layer acts as a solder barrier and the Group VIII metal interconnect is compatible with the silicon substrate so that packaging processing steps, including lead soldering, can be carried out, and the chip electrically tested, in the semiconductor fabrication facility.

Abstract: Interconnect or metallization structures for integrated circuits on semiconductor chips contain blocked conductor segments to limit atomic transport from one segment to another thus minimizing stress migration and electromigration damage. Since the blocked conductor segments prevent atomic transport between two neighboring segments, the total amount of atoms and vacancies available for hillock and void growth in a segment can be controlled by the length of the segment. The conductor segments are made of high electrical conductance metals, such as aluminum, copper or gold based alloys, and are separated by very short segments of a high melting temperature refractory metal or alloy. Because of their high melting temperatures, refractory metals or alloys suppress atomic transport. The interconnect structures can be fabricated by conventional lithographic and deposition techniques.