Abstract: Driving circuit comprises a first input, at which a first supply voltage is present, a second input, at which a second supply voltage is present, a first current supply unit selectively coupled to first or second input as function of at least one first control signal, at least one second current supply unit selectively coupled to first or second input as function of at least one second control signal, a control unit connected to first current supply unit and to at least one second current supply unit for respective control thereof and designed to provide at least one first and second control signal, and a first output coupled to first current supply unit to provide a first current for at least one first light-emitting diode, at least one second output coupled to at least one second current supply unit to provide second current for at least one second light-emitting diode.

Abstract: Driving circuit comprises a first input, at which a first supply voltage is present, a second input, at which a second supply voltage is present, a first current supply unit selectively coupled to first or second input as function of at least one first control signal, at least one second current supply unit selectively coupled to first or second input as function of at least one second control signal, a control unit connected to first current supply unit and to at least one second current supply unit for respective control thereof and designed to provide at least one first and second control signal, and a first output coupled to first current supply unit to provide a first current for at least one first light-emitting diode, at least one second output coupled to at least one second current supply unit to provide second current for at least one second light-emitting diode.

Abstract: A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).

Abstract: The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.

Abstract: A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).

Abstract: The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.