Abstract: Provides evaluation and management of system resources in a data processing system, particularly in a SoC device and for optimizing the operation of the system wherein the system having a plurality of components each operable to process dedicated tasks in the data processing system, wherein each of the components has its associated current resource usages depending on the currently processed task and/or its future resource usage depending on the tasks to be processed next, wherein the resource usage indicates the type of resources and the amount of resources used, wherein the processing of the task of at least one of the components can be modified to adapt the resource usage of this or other component. A method including: determining operating states; estimating current and future resource usage; if necessary adapting task processing according to a predefined scheme to reduce the-resource usage.

Abstract: A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.

Abstract: A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.

Abstract: Cooling structure for direct heat transfer between an active layer of a chip in which electric elements are formed and a heat sink are disclosed. The inventive cooling structure consists of a current/voltage supply level, with metal structures and insulation spacers and/or layers, partly covered by an insulation layer and followed by a heat transfer structure. A heat transfer bridge is in thermal connection with the heat transfer structure that provides for heat flux between the inventive cooling structure and the heat sink. The inventive cooling structure of this invention can be used with semiconductor devices and/or with opto-electronic devices.

Abstract: Optoelectronic composite consisting of two chips, the first chip 10 being made of a first material, the second one 13 being made of another material. The first chip 10, for example, comprises a multiplicity of active optoelectronic devices e.g. a laser diode 11 and a photo diode 12, all being monolithically integrated. A multiplicity of other optical devices, e.g. a waveguide 16, is monolithically integrated on the second chip 13. In addition this second chip 13 has depressions of the size of the devices 11,12 integrated on said first chip 10. These devices and the waveguide 16 of the second chip 13 are automatically aligned when flipping both chips together.

Abstract: Cooling structure for direct heat transfer between an active layer of a chip in which electric elements are formed and a heat sink are disclosed. The inventive cooling structure consists of a current/voltage supply level, with metal structures and insulation spacers and/or layers, partly covered by an insulation layer and followed by a heat transfer structure. A heat transfer bridge is in thermal connection with the heat transfer structure that provides for heat flux between the inventive cooling structure and the heat sink. The inventive cooling structure of this invention can be used with semiconductor devices and/or with opto-electronic devices.