Patents by Inventor Peter C. C. Hsue

Peter C. C. Hsue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of making self-aligned double density polysilicon lines for EPROM
    Patent number: 5310693
    Abstract: A method of forming a closely spaced self-aligned polysilicon pattern of conductive lines is achieved. The method involves forming semiconductor device structures in and on a semiconductor substrate. An insulating layer is formed over the device structures. An insulating layer structure is formed over the semiconductor device structures. A conductive polysilicon layer is formed over the insulating layer. A silicon oxide layer is formed over the polysilicon layer. The oxide layer is now patterned by lithography and etching. The patterning of the oxide layer leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines.
    Type: Grant
    Filed: June 24, 1993
    Date of Patent: May 10, 1994
    Assignee: United Microelectronics Corporation
    Inventor: Peter C. C. Hsue
  • Self-aligned double density polysilicon lines for ROM and EPROM
    Patent number: 5236853
    Abstract: A method of forming a closely spaced self-aligned polysilicon pattern of conductive lines is achieved. The method involves forming semiconductor device structures in and on a semiconductor substrate. An insulating layer is formed over the device structures. An insulating layer structure is formed over the semiconductor device structures. A conductive polysilicon layer is formed over the insulating layer. A silicon oxide layer is formed over the polysilicon layer. The oxide layer is now patterned by lithography and etching. The patterning of the oxide layer leaves a first pattern of the oxide over a first designated plurality of polysilicon conductor lines and a second pattern between the oxide which exposes the polysilicon layer over a second designated plurality of polysilicon conductor lines plus the planned spacing between the first and second plurality of polysilicon conductor lines.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: August 17, 1993
    Assignee: United Microelectronics Corporation
    Inventor: Peter C. C. Hsue