Abstract: In a computer system, a memory system has a memory structure and means whereby the smallest memory unit, the RAM chip, may be addressed and accessed twice during each clock cycle.

Abstract: A write amplifier for a computer memory unit features a first and a second output terminal. The amplifier may be controlled, in the write mode, to provide output signals, on the two output terminals, of one relative polarity or the other in accordance with an applied data signal. The amplifier may be further controlled, in the read mode, to provide substantially identical signals, called a read reference voltage level, on both output terminals.

Abstract: An improved multiword data register array which features RAM technology to provide a greater memory capacity in a smaller space than a conventional register arrays. Whereas RAM technology does not ordinarily include the capability of simultaneously reading and writing, in accordance with the present invention, data may be written into the register on a first half cycle of a clock signal and read out of memory on the second half cycle of the same clock signal. If the writing and the reading of the data relate to the same address in the register array, the data may be read directly from the input circuit.

Abstract: A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop is connected around the first stage. The negative feedback loop enhances the response characteristic of the amplifier. Circuit means are also provided which enables the selective steering of energizing current through or away from the second stage of the differential amplifier to provide for the selective blocking of the output of the sense amplifier.

Abstract: A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted input signals, for generating a plurality of logical product terms. A programmable sum array combines the plurality of product terms to generate a plurality of sum terms, each of the plurality of sum terms being an output of the programmable circuit array. Test logic is included which selectively causes each of the product terms, the equivalent input signals, and the inverted input signals to have a predetermined logic state in response to at least one control signal.

Abstract: The present invention relates to a dynamically testable programmable logic array in an unprogrammed state which adds some circuit components to the static test logic. The static test logic provides the capability to detect stuck-at faults at the input of each logic gate of the programmable logic array, and is inoperative during normal operation of the programmable logic array. The added circuit components cause selected inputs to the product array to partially enable the product array, whereby the remaining inputs to the product array are a function of the inputs to the programmable logic array, thereby providing the dynamic test capability.