Patents by Inventor Peter C. Elmendorf
Peter C. Elmendorf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10372851Abstract: A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.Type: GrantFiled: May 11, 2017Date of Patent: August 6, 2019Assignee: International Business Machines CorporationInventors: Nathan Buck, Sean M. Carey, Peter C. Elmendorf, Eric A. Foreman, Jeffrey G. Hemmett, Lyle Jackson, Kerim Kalafala, Stephen G. Shuma, Michael H. Wood
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Publication number: 20180330032Abstract: A design and timing model for at least one circuit path of at least a portion of an IC design is loaded into a computer. At least one canonical clock variable associated with the model is defined; it includes at least one source of variation. The computer is used to perform an SSTA of the at least one circuit path, based on the design and timing model and the at least one canonical clock variable, to obtain slack canonical data. A clock period is projected, based on the slack canonical data, such that a cycle time canonical is projected to a different space than a logic canonical. Results of the SSTA and the projected clock period are output to determine performance compliance. Efficient operation of the computer is enhanced by analyzing a slack vector in a single timing run, loaded once, and multithreading timing propagation.Type: ApplicationFiled: May 11, 2017Publication date: November 15, 2018Inventors: Nathan Buck, Sean M. Carey, Peter C. Elmendorf, Eric A. Foreman, Jeffrey G. Hemmett, Lyle Jackson, Kerim Kalafala, Stephen G. Shuma, Michael H. Wood
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Patent number: 9922149Abstract: A method, system, and computer program product to integrate functional analysis and common path pessimism removal (CPPR) in static timing analysis include determining initial path slack for a path for a given timing analysis test. The method also includes comparing the initial path slack with a threshold value to determine if the path passes or fails the given timing analysis test, and based on the path failing the given timing analysis test, performing the functional analysis on the path only based on performing the CPPR on the path, or performing the CPPR on the path only based on a result of performing the functional analysis on the path.Type: GrantFiled: April 19, 2016Date of Patent: March 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter C. Elmendorf, Kerim Kalafala, Stephen G. Shuma, Alexander J. Suess
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Patent number: 9798850Abstract: Aspects relate to a computer implemented method for timing analysis and pessimism removal of an integrated circuit. The computer implemented method includes performing, using a processor, a static timing analysis of the integrated circuit and generating timing data, generating a light weight path signature of a path using the generated timing data, performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information, and storing, in a storage medium, the light weight path signature and the corresponding CPPR information. The method also includes generating a timing report using the light weight path signature and the corresponding CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature, and reporting the timing report with full path details and corresponding CPPR information.Type: GrantFiled: January 5, 2016Date of Patent: October 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter C. Elmendorf, Kerim Kalafala, Prabhat Maurya
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Publication number: 20170193152Abstract: Aspects relate to a computer implemented method for timing analysis and pessimism removal of an integrated circuit. The computer implemented method includes performing, using a processor, a static timing analysis of the integrated circuit and generating timing data, generating a light weight path signature of a path using the generated timing data, performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information, and storing, in a storage medium, the light weight path signature and the corresponding CPPR information. The method also includes generating a timing report using the light weight path signature and the corresponding CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature, and reporting the timing report with full path details and corresponding CPPR information.Type: ApplicationFiled: January 5, 2016Publication date: July 6, 2017Inventors: Peter C. Elmendorf, Kerim Kalafala, Prabhat Maurya
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Publication number: 20170147739Abstract: A method, system, and computer program product to integrate functional analysis and common path pessimism removal (CPPR) in static timing analysis include determining initial path slack for a path for a given timing analysis test. The method also includes comparing the initial path slack with a threshold value to determine if the path passes or fails the given timing analysis test, and based on the path failing the given timing analysis test, performing the functional analysis on the path only based on performing the CPPR on the path, or performing the CPPR on the path only based on a result of performing the functional analysis on the path.Type: ApplicationFiled: April 19, 2016Publication date: May 25, 2017Inventors: Peter C. Elmendorf, Kerim Kalafala, Stephen G. Shuma, Alexander J. Suess
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Patent number: 9418201Abstract: A method, system, and computer program product to integrate functional analysis and common path pessimism removal (CPPR) in static timing analysis include determining initial path slack for a path for a given timing analysis test. The method also includes comparing the initial path slack with a threshold value to determine if the path passes or fails the given timing analysis test, and based on the path failing the given timing analysis test, performing the functional analysis on the path only based on performing the CPPR on the path, or performing the CPPR on the path only based on a result of performing the functional analysis on the path.Type: GrantFiled: November 19, 2015Date of Patent: August 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter C. Elmendorf, Kerim Kalafala, Stephen G. Shuma, Alexander J. Suess
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Patent number: 9235458Abstract: A method of delegating work of a computer program across a mixed computing environment is provided. The method includes: performing on one or more processors: allocating a container structure on a first context; delegating a new operation to a second context based on the container; receiving the results of the new operation; and storing the results in the container.Type: GrantFiled: January 6, 2011Date of Patent: January 12, 2016Assignee: International Business Machines CorporationInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Chen Luo
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Patent number: 9052968Abstract: A method of linking a computer program across a mixed computing environment is provided. The method includes, performing on one or more processors: identifying signatures of elements of the computer program; loading a plurality of modules of the computer program; and linking the plurality of modules using the signatures of the elements.Type: GrantFiled: January 17, 2011Date of Patent: June 9, 2015Assignee: International Business Machines CorporationInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Chen Luo
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Patent number: 8943475Abstract: A method of debugging a computer program across a mixed computing environment is provided. The method includes attaching a first debug module to a first program module of the computer program, where the first program module is operating on a first node; attaching a second debug module to a second program module of the computer program, where the second program module operating a second node of a different computer architecture; and initiating debug functions of at least one of the first debug module and the second debug module through a distant linker.Type: GrantFiled: January 17, 2011Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Chen Luo
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Publication number: 20120185837Abstract: A method of linking a computer program across a mixed computing environment is provided. The method includes, performing on one or more processors: identifying signatures of elements of the computer program; loading a plurality of modules of the computer program; and linking the plurality of modules using the signatures of the elements.Type: ApplicationFiled: January 17, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Chen Luo
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Publication number: 20120185828Abstract: A method of debugging a computer program across a mixed computing environment is provided. The method includes attaching a first debug module to a first program module of the computer program, where the first program module is operating on a first node; attaching a second debug module to a second program module of the computer program, where the second program module operating a second node of a different computer architecture; and initiating debug functions of at least one of the first debug module and the second debug module through a distant linker.Type: ApplicationFiled: January 17, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Chen Luo
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Publication number: 20120185677Abstract: A method of managing binary data across a mixed computing environment is provided. The method includes performing on one or more processors: receiving binary data; receiving binary coded data indicating a type of the binary data; formatting the binary data and the binary coded data according to a first format; and generating at least one of a message and a file based on the formatted data.Type: ApplicationFiled: January 14, 2011Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Luo Chen
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Publication number: 20120180054Abstract: A method of delegating work of a computer program across a mixed computing environment is provided. The method includes: performing on one or more processors: allocating a container structure on a first context; delegating a new operation to a second context based on the container; receiving the results of the new operation; and storing the results in the container.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harry J. Beatty, III, Peter C. Elmendorf, Charles Gates, Chen Luo
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Patent number: 7140018Abstract: A method of parallel processing in which there is first provided a first thread which represents an independent flow of control managed by a program structure, the first thread having two states, a first state processing work for the program structure and a second state undispatched awaiting work to process; and a second thread which represents an independent flow of control managed by a program structure separate from the first thread. The method includes using the second thread to prepare work for the first thread to process and placing the work prepared by the second thread in a queue for processing by the first thread. If the first thread is awaiting work to process when the work prepared by the second thread is placed in the queue, the method includes dispatching the first thread and using it to process the work in the queue.Type: GrantFiled: June 20, 2000Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Harry J. Beatty, III, Peter C. Elmendorf
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Patent number: 7031989Abstract: A method is described for dynamic stitching of a new module of executable code in a parallel processing environment, where access to a data object is shared by the new module and another module previously loaded. A new data object is created for shared access by the new module and by the other module; a data freshness indicator is updated in accordance therewith. A pointer value for the data pointer associated with the other module is modified, thereby terminating reference to an old data object previously accessed and substituting reference to the new data object. A second data freshness indicator is updated in accordance with access by the other module to the new data object. The old data object is deleted when a comparison between freshness indicators shows that access to the old data object is no longer required.Type: GrantFiled: February 26, 2001Date of Patent: April 18, 2006Assignee: International Business Machines CorporationInventors: Peter C. Elmendorf, Unmesh A. Ballal, Harry J. Beatty, III, Qi Yan
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Patent number: 6832378Abstract: A computer memory structure for parallel computing has a first level of hierarchy comprising a plane. The plane contains a thread which represents an independent flow of control managed by a program structure, a heap portion for data structure, a stack portion for function arguments, and local variables and global data accessible by any part of the program structure. The memory structure further has a second level of hierarchy comprising a space. The space contains two or more of the planes, with the planes in the space containing the program structure. The space further contains common data accessible by the program structure between each of the planes. A third level of hierarchy in the memory structure comprises two or more of the spaces. The spaces contain the same or different program structures, and common data accessible by the program structure between each of the spaces.Type: GrantFiled: June 20, 2000Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Harry J. Beatty, III, Peter C. Elmendorf
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Patent number: 6507903Abstract: A method for allocating memory in a parallel processing computing system in which there is first provided a system memory available for parallel processing and first and second threads, each of the threads representing an independent flow of control managed by a program structure and performing different program tasks. The method includes using the first thread to request memory from the system memory; allocating to the first thread a first pool of memory in excess of the request and associating the memory pool with the second thread; using the second thread to request memory from the system memory; allocating to the second thread a second pool of memory in excess of the request and associating the memory pool with the first thread; using the first thread to request further memory from the second thread; and allocating to the first thread a portion of the second pool of memory from the second thread without making a request to the system memory.Type: GrantFiled: June 20, 2000Date of Patent: January 14, 2003Assignee: International Business Machines CorporationInventors: Harry J. Beatty, III, Peter C. Elmendorf
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Publication number: 20020120601Abstract: A method is described for dynamic stitching of a new module of executable code in a parallel processing environment, where access to a data object is shared by the new module and another module previously loaded. A new data object is created for shared access by the new module and by the other module; a data freshness indicator is updated in accordance therewith. A pointer value for the data pointer associated with the other module is modified, thereby terminating reference to an old data object previously accessed and substituting reference to the new data object. A second data freshness indicator is updated in accordance with access by the other module to the new data object. The old data object is deleted when a comparison between freshness indicators shows that access to the old data object is no longer required.Type: ApplicationFiled: February 26, 2001Publication date: August 29, 2002Inventors: Peter C. Elmendorf, Unmesh A. Ballal, Harry J. Beatty, Qi Yan
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Patent number: 5615127Abstract: In order to efficiently execute a complex task within a computer system, the task is partitioned into a plurality of entities. A master process and a slave process are started for each entity. The master processes schedule operations to be performed, while the slave processes perform the operations. One slave process is coupled to one or more other slave processes because of path interconnections between the entities. Communication is established between any coupled slave processes such that one slave process may directly communicate with another slave process without involving the master processes. The master and slave processes execute in parallel on a plurality of processors.Type: GrantFiled: November 30, 1994Date of Patent: March 25, 1997Assignee: International Business Machines CorporationInventors: Harry J. Beatty, Peter C. Elmendorf, Roland R. Gillis, Ira Pramanick