Patents by Inventor Peter C. Norwood

Peter C. Norwood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5317752
    Abstract: A fault-tolerant computer system employs a power supply system including a battery backup so that upon AC power failure the system can execute an orderly shutdown, saving state to disk. A restart procedure restores the state existing at the time of power failure if the AC power has been restored by the time the shutdown is completed. This powerfail/autorestart procedure may be implemented in a fault-tolerant multiprocessor configuration having multiple identical CPUs executing the same instruction stream, with multiple, identical memory modules in the address space of the CPUs storing duplicates of the same data. The system detects faults in the CPUs and memory modules, and places a faulty unit offline while continuing to operate using the good units.
    Type: Grant
    Filed: November 16, 1992
    Date of Patent: May 31, 1994
    Assignee: Tandem Computers Incorporated
    Inventors: Douglas E. Jewett, Phil Webster, Dave Aldridge, Peter C. Norwood, Nikhil A. Mehta
  • Patent number: 5193175
    Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.
    Type: Grant
    Filed: March 6, 1991
    Date of Patent: March 9, 1993
    Assignee: Tandem Computers Incorporated
    Inventors: Richard W. Cutts, Jr., Peter C. Norwood, Kenneth C. DeBacker, Nikhil A. Mehta, Douglas E. Jewett, John D. Allison, Robert W. Horst