Abstract: A platform for creating an artificial blood brain barrier including a functional, perfused artificial vessel lined with endothelial cells embedded in a physiologically relevant three-dimensional extracellular matrix is described.

Abstract: A platform for creating an artificial blood brain barrier including a functional, perfused artificial vessel lined with endothelial cells embedded in a physiologically relevant three-dimensional extracellular matrix is described.

Abstract: Applications in nanomedicine, such as diagnostics and targeted therapeutics, rely on the detection and targeting of membrane biomarkers. Disclosed herein are functionalized quantum dots exhibiting greater stability in water, methods of making the functionalized quantum dots and methods of in vivo imaging using the functionalized quantum dots.

Abstract: Applications in nanomedicine, such as diagnostics and targeted therapeutics, rely on the detection and targeting of membrane biomarkers. The present invention, in one embodiment, utilizes quantitative profiling, spatial mapping, and multiplexing of cancer biomarkers using functionalized quantum dots. This approach provides highly selective targeting molecular markers for pancreatic cancer with extremely low levels of non-specific binding and provides quantitative spatial information of biomarker distribution on a single cell, which is important since tumors cell populations are inherently heterogeneous. The quantitative measurements (number of molecules per square micron) is validated using flow cytometry and demonstrated using multiplexed quantitative profiling using color-coded quantum dots.

Abstract: The invention provides multisegmented, multifunctional magnetic nanowires for the probing and manipulation of molecules at the cellular and subcellular level. The different segments of the nanowire may have differing properties, including a variety of magnetic, non-magnetic, and luminescent behavior. Differences in surface chemistry allow different segments of a single nanowire to be functionalized with different multiple functional groups and/or ligands, giving the wire chemical multifunctionality.

Abstract: The invention provides multisegmented, multifunctional magnetic nanowires for the probing and manipulation of molecules at the cellular and subcellular level. The different segments of the nanowire may have differing properties, including a variety of magnetic, non-magnetic, and luminescent behavior. Differences in surface chemistry allow different segments of a single nanowire to be functionalized with different multiple functional groups and/or ligands, giving the wire chemical multifunctionality.

Abstract: The invention is directed to the use of electrochemical deposition to fabricate thin films of a material (e.g., bismuth) exhibiting a superior magnetoresistive effect. The process in accordance with a preferred embodiment produces a thin film of bismuth with reduced polycrystallinization and allows for the production of single crystalline thin films. Fabrication of a bismuth thin film in accordance with a preferred embodiment of the invention includes deposition of a bismuth layer onto a substrate using electrochemical deposition under relatively constant current density. Preferably, the resulting product is subsequently exposed to an annealing stage for the formation of a single crystal bismuth thin film. The inclusion of these two stages in the process produces a thin film exhibiting superior MR with a simple field dependence in the process suitable for a variety of field sensing applications.

Abstract: The invention is directed to the use of copper as via and interconnect structures for an integrated circuit. The process in accordance with a preferred embodiment produces an interconnect layer of continuous copper with superior adhesion while requiring only a minimum number of steps for its production. This process addresses the current need in semiconductor manufacturing for reliable and performance-oriented vias and interconnect structures, while not being susceptible to many of the problems which plague the use of aluminum for similar structures. Fabrication of an integrated circuit in accordance with a preferred embodiment of the invention begins with the formation of semiconductor devices on a silicon wafer. Next, an intermetallic dielectric layer (IDL) is formed by materials such as silicon dioxide (SiO2), polymide, or silicon nitride over the devices. This step is followed by the laying of a diffusion barrier layer on the IDL surface.

Abstract: The invention is directed to the use of copper as via and interconnect structures for an integrated circuit. The process in accordance with a preferred embodiment produces an interconnect layer of continuous copper with superior adhesion while requiring only a minimum number of steps for its production. This process addresses the current need in semiconductor manufacturing for reliable and performance-oriented vias and interconnect structures, while not being susceptible to many of the problems which plague the use of aluminum for similar structures. Fabrication of an integrated circuit in accordance with a preferred embodiment of the invention begins with the formation of semiconductor devices on a silicon wafer. Next, an intermetallic dielectric layer (IDL) is formed by materials such as silicon dioxide (SiO2), polymide, or silicon nitride over the devices. This step is followed by the laying of a diffusion barrier layer on the IDL surface.

Abstract: An electron-emitting device contains a lower conductive region (22), a porous insulating layer (24A, 24B, 24D, 24E, or 24F) overlying the lower conductive region, and a multiplicity of electron-emissive elements (30, 30A, or 30B) situated in pores (281) extending through the porous layer. The pores are situated at locations substantially random relative to one another. The lower conductive region typically contains a highly conductive portion (22A) and an overlying highly resistive portion (22B). Alternatively or additionally, a patterned gate layer (34B, 40B, or 46B) overlies the porous layer. Openings (36, 42, or 541) corresponding to the filaments extend through the gate layer at locations generally centered on the filaments such that the filaments are separated from the gate layer.

Abstract: Novel arrays of nanowires made of semi-metallic Bismuth (Bi) is disclosed made by unique electrodeposition techniques. Because of the unusual electronic properties of the semi-metallic Bi and the nanowire geometry, strong finite size effects in transport properties are achieved. In addition, very large positive magnetoresistance, 300% at low temperatures and 70% at room temperature, with quasilinear field dependence have been attained.

Abstract: An apparatus and method is disclosed; both of which use electrochemistry to selectively grow and remove hard oxide coatings on metals, and capacitive double layers on non-metals and semiconductors in order to predict and control the rate of surface abrasion during planarization of the surface of such materials.

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract: An impedance-assisted electrochemical method is employed for selectively removing certain material from a structure without significantly electrochemically removing certain other material of the same chemical type as the removed material.

Abstract: A field-emission structure suitable for large-area flat-panel televisions centers around an insulating porous layer that overlies a lower conductive region situated over insulating material of a supporting substrate. Electron-emissive filaments occupy pores extending through the porous layer. A conductive gate layer through which openings extend at locations centered on the filaments typically overlies the porous layer. Cavities are usually provided in the porous layer along its upper surface at locations likewise centered on the filaments.

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract: An electrochemical technique is employed for removing certain material from a partially finished structure without significantly chemically attacking certain other material of the same chemical type as the removed material. The partially finished structure contains a first electrically non-insulating layer (52C) consisting at least partially of first material, typically excess emitter material that accumulates during the deposition of the emitter material to form electron-emissive elements (52A) in an electron emitter, that overlies an electrically insulating layer (44). An electrically non-insulating member, such as an electron-emissive element, consisting at least partially of the first material is situated at least partly in an opening (50) extending through the insulating layer.

Abstract: This invention provides a method for producing a quasi-solid state charge storage device capable of being repeatedly charged and discharged, having one or more electrochemical cells with a structure capable of being stacked or combined to form primary or secondary battery devices, each cell composed entirely of an ionically conducting gel polymer electrolyte layer separating opposing surfaces of electronically conducting conjugated polymeric anode and cathode electrodes supported on lightweight porous substrates; a method of forming conjugated polymers into large area composite electrode structures with practical levels of charge storage capacity; and a quasi-solid state charge storage device produced by the above methods.

Abstract: Gated electron emitters are fabricated by processes in which charged particles are passed through a track layer (24, 48, or 144) to form charged-particle tracks (26.sub.1, 50.sub.1, or 146.sub.1). The track layer is etched along the tracks to create open spaces (28.sub.1, 52.sub.1, or 148.sub.1). Electron-emissive elements (30 or 142D) can then be formed at locations respectively centered on the open spaces after which a patterned gate layer (34B, 40B, or 158C) is provided. Alternatively, the open spaces in the track layer can be employed to etch corresponding apertures (54.sub.1) through an underlying non-insulating layer (46) which typically serves as the gate layer. An etch is performed through the apertures to form dielectric open spaces (56.sub.1, 96.sub.1, or 114.sub.1) in an insulating layer (24) that lies below the non-insulating layer. Electron-emissive elements (30B, 30/88D.sub.1, 98/102.sub.1, or 118.sub.1) can subsequently be provided, typically in the dielectric open spaces.

Abstract: A field-emission structure suitable for large-area flat-panel televisions centers around an insulating porous layer (24A) that overlies a lower conductive region (22) situated over insulating material of a supporting substrate (20). Electron-emissive filaments (30) occupy pores (28) extending through the porous layer. A conductive gate layer (34A) through which openings (36) extend at locations centered on the filaments typically overlies the porous layer. Cavities (38) are usually provided in the porous layer along its upper surface at locations likewise centered on the filaments.In fabricating the structure, the pores are preferably formed by etching charged-particle tracks. Electrochemical deposition is employed to selectively create the filaments in the pores. Self-alignment of the gate openings to the filaments is achieved with charged-particle track etching and/or further electrochemical processing.