Patents by Inventor Peter C. Tong

Peter C. Tong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7483032
    Abstract: Circuits, methods, and apparatus that allow the elimination of a frame buffer connected directly to a graphics processing unit. The graphics processing unit includes an on-chip memory. Following system power-up or reset, the GPU initially renders comparatively low-resolution images to the on-chip memory for display. Afterward, the GPU renders images, which are typically higher resolution, and stores them in a system memory, apart from the graphics processing unit. The on-chip memory, which is no longer needed for image storage, instead stores address information, referred to as page tables, identifying the location of data stored by the GPU in the separate system memory.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: January 27, 2009
    Assignee: NVIDIA Corporation
    Inventors: Sonny S. Yeoh, Shane J. Keil, Dennis K. Ma, Peter C. Tong
  • Patent number: 7415575
    Abstract: A cache shared by multiple clients implements a client specific policy for replacing entries in the event of a cache miss. A request from any client can hit any entry in the cache. For purposes of replacing entries, at least of the clients is restricted, and when a cache miss results from a request by the restricted client, the entry to be replaced is selected from a fixed subset of the cache entries. When a cache misses results from a request by any client other than the restricted client, any cache entry, including a restricted entry, can be selected to be replaced.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: August 19, 2008
    Assignee: NVIDIA, Corporation
    Inventors: Peter C. Tong, Colyn S. Case
  • Publication number: 20080028181
    Abstract: Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.
    Type: Application
    Filed: March 21, 2007
    Publication date: January 31, 2008
    Applicant: NVIDIA Corporation
    Inventors: Peter C. Tong, Sonny S. Yeoh, Kevin J. Kranzusch, Gary D. Lorensen, Kaymann L. Woo, Ashish Kishen Kaul, Colyn S. Case, Stefan A. Gottschalk, Dennis K. Ma
  • Patent number: 5581473
    Abstract: A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: December 3, 1996
    Assignee: Sun Microsystems, Inc.
    Inventors: Stefan Rusu, Stuart A. Taylor, Peter C. Tong, Gregory Schulte