Patents by Inventor Peter Caputa
Peter Caputa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250070714Abstract: A tank circuit includes a tunable resonator subcircuit having an effective parallel resistance that varies with tuning of the tunable resonator subcircuit. The tank circuit further comprises a variable negative-resistance subcircuit coupled in parallel to the tunable resonator subcircuit, where the variable negative-resistance subcircuit is configured to provide a variable negative resistance, so as to increase the effective parallel resistance of the tank circuit. A control circuit is configured to increase the negative resistance presented by the variable negative-resistance subcircuit in response to a change in the tunable resonator subcircuit that lowers the resonant frequency of the tunable resonator subcircuit.Type: ApplicationFiled: August 12, 2024Publication date: February 27, 2025Inventors: Ufuk Özdemir, Peter Caputa, Mustafa Özen, Ahmed Mahmoud
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Patent number: 12088252Abstract: A tank circuit (200) includes a tunable resonator subcircuit (210) having a first control input and having an effective parallel resistance that varies with tuning of the tunable resonator subcircuit (210). The tank circuit (200) further comprises a variable negative-resistance subcircuit (250) having a second control input and coupled in parallel to the tunable resonator subcircuit (210), where the variable negative-resistance subcircuit (250) is configured to provide a variable negative resistance, responsive to the control input, so as to increase the effective parallel resistance of the tank circuit (200).Type: GrantFiled: January 30, 2019Date of Patent: September 10, 2024Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Ufuk Özdemir, Peter Caputa, Mustafa Özen, Ahmed Mahmoud
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Publication number: 20240259043Abstract: An interface port (10) for a bidirectional interface is presented. The interface port (10) comprises an input terminal (12) operatively connected to an input of a first active inductor (100), an output terminal (13) operatively connected to an output of a second active inductor (200), and a bidirectional terminal (11) operatively connected to an output of the first active inductor (100) and to an input of the second active inductor (200). Each of the first and second active inductor (100, 200) respectively comprises a forward transconductance stage and a feedback transconductance stage. An associated electric circuitry, electronic apparatus, electric system and a method of control are also disclosed.Type: ApplicationFiled: May 12, 2021Publication date: August 1, 2024Applicant: Telefonaktiebolaget LM Ericsson (pub)Inventors: Ufuk ÖZDEMIR, Kirill KOZMIN, Peter CAPUTA
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Patent number: 12028033Abstract: A filter circuitry (200) using an active inductor is disclosed. The filter circuitry (200) has a first terminal (In1/Out1) and a second terminal (In2/Out2). The filter circuitry (200) comprises a first transistor (M1) and a second transistor (M2). The filter circuitry (200) further comprises a first switch (S1), a second switch (S2), a first capacitor (C1), a second capacitor (C2) and a resistor (R). The first and second transistors (M1/M2) together with the resistor (R) and the first and second switches (S1/S2) are connected in a current mirror topology. The first and second capacitors (C1/C2) are connected at the first and second terminals of the filter circuitry (200) respectively. The filter circuitry (200) is configurable to either have the first terminal (In1/Out1) as input and the second terminal (In2/Out2) as output or have the first terminal (In1/Out1) as output and the second terminal (In2/Out2) as input by changing on-off states of the first and second switches.Type: GrantFiled: May 20, 2020Date of Patent: July 2, 2024Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventors: Ufuk Özdemir, Peter Caputa, Kirill Kozmin
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Publication number: 20230188118Abstract: A filter circuitry (200) using an active inductor is disclosed. The filter circuitry (200) has a first terminal (In1/Out1) and a second terminal (In2/Out2). The filter circuitry (200) comprises a first transistor (M1) and a second transistor (M2). The filter circuitry (200) further comprises a first switch (S1), a second switch (S2), a first capacitor (C1), a second capacitor (C2) and a resistor (R). The first and second transistors (M1/M2) together with the resistor (R) and the first and second switches (S1/S2) are connected in a current mirror topology. The first and second capacitors (C1/C2) are connected at the first and second terminals of the filter circuitry (200) respectively. The filter circuitry (200) is configurable to either have the first terminal (In1/Out1) as input and the second terminal (In2/Out2) as output or have the first terminal (In1/Out1) as output and the second terminal (In2/Out2) as input by changing on-off states of the first and second switches.Type: ApplicationFiled: May 20, 2020Publication date: June 15, 2023Inventors: Ufuk Özdemir, Peter Caputa, Kirill Kozmin
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Publication number: 20220085759Abstract: A tank circuit (200) includes a tunable resonator subcircuit (210) having a first control input and having an effective parallel resistance that varies with tuning of the tunable resonator subcircuit (210). The tank circuit (200) further comprises a variable negative-resistance subcircuit (250) having a second control input and coupled in parallel to the tunable resonator subcircuit (210), where the variable negative-resistance subcircuit (250) is configured to provide a variable negative resistance, responsive to the control input, so as to increase the effective parallel resistance of the tank circuit (200).Type: ApplicationFiled: January 30, 2019Publication date: March 17, 2022Inventors: Ufuk Özdemir, Peter Caputa, Mustafa Özen, Ahmed Mahmoud
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Patent number: 7708619Abstract: A method of producing a complex shape in a workpiece includes the steps of: i) grinding a workpiece at a maximum specific cutting energy of about 10 Hp/in3·min with at least one bonded abrasive tool, thereby forming a slot in the workpiece; and ii) grinding the slot with at least one mounted point tool, thereby producing the complex shape in the slot. The bonded abrasive tool includes at least about 3 volume % of a filamentary sol-gel alpha-alumina abrasive grain having an average length-to-cross-sectional-width ratio of greater than about 4:1 or an agglomerate thereof. A method of producing a slot in a metallic workpiece having a maximum hardness value of equal to, or less than, about 65 Rc includes the step of grinding the workpiece with a bonded abrasive tool at a material removal rate in a range of between about 0.25 in3/min·in and about 60 in3/min·in and at a maximum specific cutting energy of about 10 Hp/in3·min.Type: GrantFiled: May 23, 2006Date of Patent: May 4, 2010Assignees: Saint-Gobain Abrasives, Inc., Saint-Gobain AbrasifsInventors: Krishnamoorthy Subramanian, John A. Webster, Peter Caputa, IV
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Publication number: 20070275641Abstract: A method of producing a complex shape in a workpiece includes the steps of: i) grinding a workpiece at a maximum specific cutting energy of about 10 Hp/in3·min with at least one bonded abrasive tool, thereby forming a slot in the workpiece; and ii) grinding the slot with at least one mounted point tool, thereby producing the complex shape in the slot. The bonded abrasive tool includes at least about 3 volume % of a filamentary sol-gel alpha-alumina abrasive grain having an average length-to-cross-sectional-width ratio of greater than about 4:1 or an agglomerate thereof. A method of producing a slot in a metallic workpiece having a maximum hardness value of equal to, or less than, about 65 Rc includes the step of grinding the workpiece with a bonded abrasive tool at a material removal rate in a range of between about 0.25 in3/min·in and about 60 in3/min·in and at a maximum specific cutting energy of about 10 Hp/in3·min.Type: ApplicationFiled: May 23, 2006Publication date: November 29, 2007Inventors: Krishnamoorthy Subramanian, John A. Webster, Peter Caputa
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Patent number: 7196546Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.Type: GrantFiled: December 30, 2003Date of Patent: March 27, 2007Assignee: Intel CorporationInventors: Mark A. Anders, Peter Caputa, Ram Krishnamurthy
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Patent number: 7190286Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.Type: GrantFiled: December 22, 2005Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Maged M. Ghoneima, Peter Caputa, Muhammad M. Khellah, Ram Krishnamurthy, James W. Tschanz, Yiben Ye, Vivek K. De, Yehea I. Ismail
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Publication number: 20060109028Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.Type: ApplicationFiled: December 22, 2005Publication date: May 25, 2006Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehia Ismail
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Patent number: 6992603Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.Type: GrantFiled: March 31, 2004Date of Patent: January 31, 2006Assignee: Intel CorporationInventors: Maged M. Ghoneima, Peter Caputa, Muhammad M. Khellah, Ram Krishnamurthy, James W. Tschanz, Yiben Ye, Vivek K. De, Yehea I Ismail
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Publication number: 20050225459Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.Type: ApplicationFiled: March 31, 2004Publication date: October 13, 2005Inventors: Maged Ghoneima, Peter Caputa, Muhammad Khellah, Ram Krishnamurthy, James Tschanz, Yibin Ye, Vivek De, Yehea Ismail
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Publication number: 20050148102Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.Type: ApplicationFiled: December 30, 2003Publication date: July 7, 2005Inventors: Mark Anders, Peter Caputa, Ram Krishnamurthy