Abstract: One-bit digital signal processing apparatus for generating an output one-bit signal by switching from a first to a second one-bit signal in response to a detection that m consecutive bits of the first and second signal are identical, the apparatus comprising means for varying m in dependence on the urgency of the switching operation.

Abstract: A signal processor for processing 1-bit signals comprising at least a pair of Delta Sigma Modulators (DSM) coupled in series, one of the said pair of DSMs having an signal-band noise-shaping filter characteristic complementary to the signal-band noise-shaping filter characteristic of the other of the pair of DSMs.

Abstract: Data (such as digital audio data) is reproduced from a disk medium at a variable data rate and is then converted to a constant data rate by storing the reproduced data in a buffer memory and reading out the stored data at the constant data rate. Overload of the memory is detected and the reproducing head repeats reproduction of such data from the disk medium that has not been stored. When the data is configured in blocks, memory overload can be detected by input and output block counters and a buffer space comparator which compares the input and output block counts to the memory so as to provide an indication of memory overload.When the disk medium is driven at constant speed, the storage capacity of the disk medium can be increased compared to that of a constant angular velocity with constant read/write data rate system.

Abstract: A signal processor for 1-bit signals comprises a nth order Delta-Sigma Modulator, where n is greater than or equal to 2. The Delta-Sigma Modulator comprises a first input 4A for receiving a first 1-bit signal and a second input 4B for receiving a second 1-bit signal. A quantizer Q quantises a p bit signal to 1-bit form, the requantized signal being the output signal of the processor. A plurality of signal combiners are provided. A first combiner (A1, 61, c1 b1, 71) forms the integral of the sum of the input signals and the output signal multiplied by coefficients A1, B1 and C1. At least one intermediate combiner forms the integral of the sum of the first and second input signals and the output signal multiplied by coefficients A2, B2, C2 together with the output of the first combiner. The final combiner a4, b4, 64 forms the integral of the sum of the first and second signals multiplied by coefficients A4 and B4 together with the output of the preceding intermediate combiner.

Abstract: A 1-bit signal (44) is compressed (40, 41) by dividing it into a series of n-bit words and encoding the words according to the probability of their occurrence.

Abstract: An nth order Delta Sigma Modulator (DSM) where n.gtoreq.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.

Abstract: Apparatus for analyzing audio signals from a stereo pair of audio channels, comprises: means for detecting the magnitudes of the audio signals of the two audio channels; first detector for detecting a degree of phase correlation between the audio signals of the two audio channels; and second detector for generating an indicator color for display in respect of the audio channels at a time of test, the indicator color having a hue, intensity and/or saturation dependent on at least the relative magnitudes of and the degree of phase correlation between the audio signals of the two audio channels at the time of test.

Abstract: An input stage for receiving an input signal having a signal level varying to represent successive states of a one-bit digital signal, comprises: a thresholder for detecting whether the input signal level is above or below a threshold signal level; in which: the input of the thresholder is biased with a bias signal varying between a signal level above the threshold signal level and a signal level below the threshold signal level; and the amplitude of the alternating component of the bias signal is lower than the amplitude of the alternating component of the input signal.

Abstract: An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b.sub.1 to b.sub.5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b.sub.3 together with columns A and B is the truth table of an NAND gate. Column b.sub.2 together with columns A and B is the truth table of a COINCIDENCE gate.In the example of FIG. 5 column b.sub.4 equals B; column b.sub.1 is logical 0 whatever the states of A and B; and column b.sub.5 is NOT A.Thus in accordance with one illustrative embodiment of the invention the arithmetic stage 40 may be implemented by the logic circuit of FIG. 6 wherebit b.sub.5 is produced by inverting A,bit b.sub.4 is produced by coupling output b.sub.1 to input B, via a direct connection 60,bit b.sub.3 is produced by a NAND gate 61,bit b.sub.2 is produced by a COINCIDENCE gate 62, andbit b.sub.1 is produced by coupling output b.sub.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.

Abstract: Digital audio processing apparatus comprises: device for detecting the magnitude of an input digital audio signal; and a variable gain element for applying a gain to the input digital audio signal dependent on the detected magnitude of the input digital audio signal, in which:(i) the applied gain is linearly related to the envelope signal with a first predetermined slope, for detected magnitudes below a first threshold magnitude;(ii) the applied gain is linearly related to the envelope signal with a second predetermined slope, for detected magnitudes above a second threshold magnitude higher than the first threshold magnitude; and(iii) for detected magnitudes from the first threshold magnitude to the second threshold magnitude, the slope of the applied gain with respect to detected magnitude varies monotonically from the first predetermined slope to the second predetermined slope.

Abstract: Digital audio processing apparatus for applying a time-varying gain to an input digital audio signal over contiguous first, second and third time periods, in which: the applied gain changes at no more than a first maximum rate of change during the first time period; the applied gain changes at no more than a second maximum rate of change during the third time period; and during the second time period the rate of change of the applied gain varies monotonically from a substantially zero rate of change towards the second maximum rate of change.

Abstract: A loudspeaker comprises a yoke; one or more vibration driving coils disposed so as to interact magnetically with the yoke when an electrical current flows through the coils; and one or more signal amplifying devices mounted on or near the yoke, the amplifying devices being operable to receive an input audio signal, to amplify the input signal to generate an amplified signal, and to supply the amplified signal to the vibration driving coils.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the events.

Abstract: An interactive system for interfacing with signal processing apparatus having a network of interconnected processors (e.g., for a digital audio mixing console) uses a graphical user interface for monitoring the operation of the system. The graphical user interface can be used for inputting control and/or data signals at selected points in said data processing structure and/or for displaying control and/or data signals from selected points in said data processing structure in real time. A graphical representation of an audio mixing console can be used for experimentation, set-up and training purposes.

Abstract: A method and apparatus is provided for generating an interrupt signal in a data processing system, the interrupt signal being supplied to a control processor of the system to indicate the occurrence of any of a plurality of predetermined events in the system. The method and apparatus operate by: writing data to at least one memory location of a plurality of pairs of memory locations A,B of the system in dependence upon the event to be indicated, the pairs of memory locations A,B being predefined in the system for respective ones of the events; reading data from the pairs of memory locations A,B; processing the data read from each pair of memory locations A,B to generate interrupt data indicative of whether the associated event has occurred, and if so transmitting an interrupt signal to the control processor; and writing the interrupt data corresponding to the events to respective third memory locations C, the third memory locations C being predefined in the control processor for the said events.

Abstract: Digital signal processing (e.g. filtering) apparatus comprises pipelined digital signal processing means for generating each output sample of an output digital signal from input samples of an input digital signal by combining the input samples with a plurality of subsets of a set of filter coefficients associated with that output sample during a respective plurality of sample periods of the input digital signal; and coefficient generating means for supplying sets of filter coefficients to the signal processing means in response to the current state of a filter control signal. The coefficient generating means is operable to supply the plurality of subsets of each set of filter coefficients to the signal processing means during the respective plurality of sample periods of the input digital signal.