Patents by Inventor Peter Charles Eastty

Peter Charles Eastty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6281885
    Abstract: Audio processing apparatus comprises an audio processor operable to apply one or more processing operations from a set of audio processing operations to an input audio signal; adjustment controls for adjusting processing parameters associated with each of the set of processing operations; a display screen for displaying icons representing each processing operation of the set of audio processing operations; and a detector for detecting user operation of the adjustment controls associated with an a processing operation and, in response to such a detection, for displacing the display position of the icon associated with that processing operation.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: August 28, 2001
    Assignee: Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Peter Damien Thorpe, Christopher Sleight
  • Patent number: 6246773
    Abstract: In recording for example classical music played by an orchestra (O), a stereo pair (1) is used. To enhance say a quiet instrument such as a flute (F) a spot microphone (2) is used close to the flute. However, the different air-path lengths for the flute to the stereo pair (1) and spot microphone (2) creates undesired effects. The signal from the spot microphone is delayed (4), the delay being automatically controlled by an adaptive filter (5). The filter (5) correlates the spot microphone signal with the signal from the stereo pair to establish the delay time. An alternative arrangement uses an adaptive filter trained by the signal from the spot microphone to extract the flute signal from the stereo pair. In other arrangements, similar techniques are used to cancel undesired noise.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: June 12, 2001
    Assignee: Sony United Kingdom Limited
    Inventor: Peter Charles Eastty
  • Patent number: 6188344
    Abstract: A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: February 13, 2001
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 6175322
    Abstract: A signal processor for 1-bit signals comprises an nth order D Sigma Modulator (DSM) having an input (4) for receiving a 1-bit signal and an output (5) at which a processed 1-bit signal is produced by a quantizer (Q). The quantizer (Q) receives a p-bit signal from a series of 5 signal integration stages. Each stage comprises a first 1-bit multiplier (An) coupled to the input (4), a second 1-bit multiplier (Cn) coupled to the output (5), an adder (6n) which sums the outputs of the coefficient multipliers and an integrator (7n) which integrates the output of the adder (6n). A final stage comprises a coefficient multiplier (An+1) and an adder (6n+1). The adder (6n+1) sums the output of the coefficient multiplier (An+1) and the output of the integrator of the preceding integration stage. The input signal is fed to all the stages except the final stage via a 1-bit delay. The output signal of the quantizer is fed back to the stages via a 1-bit delay.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: January 16, 2001
    Assignee: Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Peter Damien Thorpe, Christopher Sleight
  • Patent number: 6167100
    Abstract: One-bit digital signal processing apparatus for generating an output one-bit signal by switching from a first to a second one-bit signal in response to a detection that m consecutive bits of the first and second signal are identical, the apparatus comprising means for varying m in dependence on the urgency of the switching operation.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: December 26, 2000
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 6144328
    Abstract: A signal processor for processing 1-bit signals comprising at least a pair of Delta Sigma Modulators (DSM) coupled in series, one of the said pair of DSMs having an signal-band noise-shaping filter characteristic complementary to the signal-band noise-shaping filter characteristic of the other of the pair of DSMs.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: November 7, 2000
    Assignee: Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Peter Damien Thorpe, Christopher Sleight
  • Patent number: 6108286
    Abstract: Data (such as digital audio data) is reproduced from a disk medium at a variable data rate and is then converted to a constant data rate by storing the reproduced data in a buffer memory and reading out the stored data at the constant data rate. Overload of the memory is detected and the reproducing head repeats reproduction of such data from the disk medium that has not been stored. When the data is configured in blocks, memory overload can be detected by input and output block counters and a buffer space comparator which compares the input and output block counts to the memory so as to provide an indication of memory overload.When the disk medium is driven at constant speed, the storage capacity of the disk medium can be increased compared to that of a constant angular velocity with constant read/write data rate system.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: August 22, 2000
    Assignee: Sony United Kingdom Limited
    Inventor: Peter Charles Eastty
  • Patent number: 6078621
    Abstract: A signal processor for 1-bit signals comprises a nth order Delta-Sigma Modulator, where n is greater than or equal to 2. The Delta-Sigma Modulator comprises a first input 4A for receiving a first 1-bit signal and a second input 4B for receiving a second 1-bit signal. A quantizer Q quantises a p bit signal to 1-bit form, the requantized signal being the output signal of the processor. A plurality of signal combiners are provided. A first combiner (A1, 61, c1 b1, 71) forms the integral of the sum of the input signals and the output signal multiplied by coefficients A1, B1 and C1. At least one intermediate combiner forms the integral of the sum of the first and second input signals and the output signal multiplied by coefficients A2, B2, C2 together with the output of the first combiner. The final combiner a4, b4, 64 forms the integral of the sum of the first and second signals multiplied by coefficients A4 and B4 together with the output of the preceding intermediate combiner.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: June 20, 2000
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 6061007
    Abstract: A 1-bit signal (44) is compressed (40, 41) by dividing it into a series of n-bit words and encoding the words according to the probability of their occurrence.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: May 9, 2000
    Assignee: Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 6057792
    Abstract: An nth order Delta Sigma Modulator (DSM) where n.gtoreq.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: May 2, 2000
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 6044223
    Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: March 28, 2000
    Assignees: Sony Corporation,, Sony United Kingdom Limited
    Inventors: Christopher Michael McCulloch, Peter Charles Eastty, William Edmund Cranstoun Kentish
  • Patent number: 6021204
    Abstract: Apparatus for analyzing audio signals from a stereo pair of audio channels, comprises: means for detecting the magnitudes of the audio signals of the two audio channels; first detector for detecting a degree of phase correlation between the audio signals of the two audio channels; and second detector for generating an indicator color for display in respect of the audio channels at a time of test, the indicator color having a hue, intensity and/or saturation dependent on at least the relative magnitudes of and the degree of phase correlation between the audio signals of the two audio channels at the time of test.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: February 1, 2000
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventor: Peter Charles Eastty
  • Patent number: 6020837
    Abstract: A 1-bit signal processor receives a 1-bit signal having a first sampling rate eg 64 fs. An upconverter (41) increases the sampling rate to eg 128 fs. A series of Delta Sigma Modulators (42, 43) processes the signal. The processed signal is down-converted by a converter (44) to 64 fs. As least the Delta Sigma Modulators may be implemented on an integrated circuit. The down-converter is arranged to prevent noise being folded back into the signal band.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: February 1, 2000
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 6002353
    Abstract: An input stage for receiving an input signal having a signal level varying to represent successive states of a one-bit digital signal, comprises: a thresholder for detecting whether the input signal level is above or below a threshold signal level; in which: the input of the thresholder is biased with a bias signal varying between a signal level above the threshold signal level and a signal level below the threshold signal level; and the amplitude of the alternating component of the bias signal is lower than the amplitude of the alternating component of the input signal.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: December 14, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 5983258
    Abstract: An arithmetic stage calculates the sum AX+BY where A and B are 1-bit signals and X and Y p bit coefficients X=7 and Y=3 and the corresponding bits b.sub.1 to b.sub.5 are represented together with the corresponding logical states of A and B. It will be seen that for example column b.sub.3 together with columns A and B is the truth table of an NAND gate. Column b.sub.2 together with columns A and B is the truth table of a COINCIDENCE gate.In the example of FIG. 5 column b.sub.4 equals B; column b.sub.1 is logical 0 whatever the states of A and B; and column b.sub.5 is NOT A.Thus in accordance with one illustrative embodiment of the invention the arithmetic stage 40 may be implemented by the logic circuit of FIG. 6 wherebit b.sub.5 is produced by inverting A,bit b.sub.4 is produced by coupling output b.sub.1 to input B, via a direct connection 60,bit b.sub.3 is produced by a NAND gate 61,bit b.sub.2 is produced by a COINCIDENCE gate 62, andbit b.sub.1 is produced by coupling output b.sub.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: November 9, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe
  • Patent number: 5964865
    Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: October 12, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Christopher Michael McCulloch, Peter Charles Eastty, William Edmund Cranstoun Kentish
  • Patent number: 5944814
    Abstract: This invention relates to the allocation of object code in multi-processor systems. In particular, techniques are disclosed for efficiently allocating signal processing instructions to a large array of parallel signal processing units.
    Type: Grant
    Filed: March 5, 1996
    Date of Patent: August 31, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Christopher Michael McCulloch, Peter Charles Eastty, William Edmund Cranstoun Kentish
  • Patent number: 5923768
    Abstract: Digital audio processing apparatus for applying a time-varying gain to an input digital audio signal over contiguous first, second and third time periods, in which: the applied gain changes at no more than a first maximum rate of change during the first time period; the applied gain changes at no more than a second maximum rate of change during the third time period; and during the second time period the rate of change of the applied gain varies monotonically from a substantially zero rate of change towards the second maximum rate of change.
    Type: Grant
    Filed: February 21, 1997
    Date of Patent: July 13, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Paul Anthony Frindle, Peter Charles Eastty
  • Patent number: 5923767
    Abstract: Digital audio processing apparatus comprises: device for detecting the magnitude of an input digital audio signal; and a variable gain element for applying a gain to the input digital audio signal dependent on the detected magnitude of the input digital audio signal, in which:(i) the applied gain is linearly related to the envelope signal with a first predetermined slope, for detected magnitudes below a first threshold magnitude;(ii) the applied gain is linearly related to the envelope signal with a second predetermined slope, for detected magnitudes above a second threshold magnitude higher than the first threshold magnitude; and(iii) for detected magnitudes from the first threshold magnitude to the second threshold magnitude, the slope of the applied gain with respect to detected magnitude varies monotonically from the first predetermined slope to the second predetermined slope.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: July 13, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Paul Anthony Frindle, Peter Charles Eastty
  • Patent number: 5912978
    Abstract: A loudspeaker comprises a yoke; one or more vibration driving coils disposed so as to interact magnetically with the yoke when an electrical current flows through the coils; and one or more signal amplifying devices mounted on or near the yoke, the amplifying devices being operable to receive an input audio signal, to amplify the input signal to generate an amplified signal, and to supply the amplified signal to the vibration driving coils.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: June 15, 1999
    Assignees: Sony Corporation, Sony United Kingdom Limited
    Inventors: Peter Charles Eastty, Christopher Sleight, Peter Damien Thorpe