Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.

Abstract: A integrated circuit system including providing an integrated circuit device, forming an undoped insulating layer over the integrated circuit device, forming a thin insulating layer over the undoped insulating layer, forming a doped insulating layer over the thin insulating layer, and forming a contact in the undoped insulating layer, thin insulating layer and the doped insulating layer.

Abstract: An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: An intermetal dielectric structure for integrated circuits and a manufacturing method therefore is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Abstract: A method for forming a thermally stable cobalt disilicide film in the fabrication of an integrated circuit is described. A semiconductor substrate is provided having silicon regions to be silicided. A cobalt layer is deposited overlying the silicon regions to be silicided. A capping layer is deposited overlying the cobalt layer. The substrate is subjected to a first rapid thermal anneal whereby the cobalt is transformed to cobalt monosilicide where it overlies the silicon regions and wherein the cobalt not overlying the silicon regions is unreacted. The unreacted cobalt layer and the capping layer are removed. A titanium layer is deposited overlying the cobalt monosilicide layer. Thereafter the substrate is subjected to a second rapid thermal anneal whereby the cobalt monosilicide is transformed to cobalt disilicide. The titanium layer provides titanium atoms which diffuse into the cobalt disilicide thereby increasing its thermal stability.

Abstract: A Method for forming a shallow trench isolation using HDP silicon oxynitride. A pad oxide layer is formed on a semiconductor substrate having an active area and an isolation area and a barc layer is formed over the pad oxide layer. The barc layer, the pad oxide layer, and the semiconductor substrate are patterned to form a trench having rounded corners in the isolation area. A liner oxide layer is formed over the semiconductor substrate, and a gap fill layer is formed on the liner oxide layer. An important feature of the invention is that the gap fill layer is composed of silicon oxynitride formed using a high density plasma chemical vapor deposition process. A portion of the gap fill layer over the active area can be removed using a reverse trench mask etch, and the gap fill layer is further planarized with a chemical mechanical polishing process using the liner oxide layer as chemical mechanical polishing stop.

Abstract: A method for forming a void-free and gap-filling doped silicon oxide insulator layer upon a patterned substrate layer within an integrated circuit. Formed upon a semiconductor substrate is a patterned substrate layer. Formed upon the patterned substrate layer is a doped silicon oxide insulator layer. The doped silicon oxide insulator layer is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method undertaken simultaneously with a Reactive Ion Etch (RIE) etch-back method. The Plasma Enhanced Chemical Vapor Deposition (PECVD) deposition method and the Reactive Ion Etch (RIE) etch-back method simultaneously employ a Tetra Ethyl Ortho Silicate (TEOS) silicon source material, a dopant source material, an oxygen source material and an etching gas.

Abstract: A method for selectively depositing WSi.sub.x is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein WSi.sub.x is to be deposited overlying a first portion of the substrate and wherein WSi.sub.x is not to be deposited overlying a second portion of the substrate. A layer of organic material is provided over the surface of the substrate overlying the second portion of the substrate. A layer of WSi.sub.x is deposited over the surface of the substrate wherein the WSi.sub.x is deposited overlying the first portion of the substrate and wherein the presence of the organic material layer prevents the WSi.sub.x from depositing overlying the second portion of the substrate completing the selective WSi.sub.x deposition in the fabrication of an integrated circuit device.