Abstract: A method for automatic power negotiation for electric vehicle-to-vehicle charge transfer, includes connecting a donor electric vehicle to a receiver electric vehicle via a charging cable of a charging cable system and receiving from a control box of the charging cable system, an initial power setting for the donor electric vehicle. The method also includes determining if the initial power setting has a non-zero value and if the initial power setting has a non-zero value, determining if the initial power setting is acceptable by the donor electric vehicle. The method further includes if the initial power setting is acceptable by the donor electric vehicle, repeatedly increasing the initial power setting to a higher power setting until a maximum power setting is determined and transferring an electric charge from the donor electric vehicle to the receiver electric vehicle along the charging cable based on the maximum power setting.

Abstract: A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the upstream unit and the downstream unit, wherein the endpoint device asserts at least one request to the upstream unit. The request scheduling method includes: transmitting the request to a processing unit while the request is a non-peer-to-peer request, and transmitting the request to a downstream unit while the request is a peer-to-peer request; wherein if the request is a peer-to-peer and posted request and there is a previous asserted request which is peer-to-peer and non-posted request and the previous asserted request has a latency exceeds a predetermined time, transmitting the request earlier than the previous asserted request to the downstream unit.

Abstract: The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.

Abstract: A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the upstream unit and the downstream unit, wherein the endpoint device asserts at least one request to the upstream unit. The request scheduling method includes: transmitting the request to a processing unit while the request is a non-peer-to-peer request, and transmitting the request to a downstream unit while the request is a peer-to-peer request; wherein if the request is a peer-to-peer and posted request and there is a previous asserted request which is peer-to-peer and non-posted request and the previous asserted request has a latency exceeds a predetermined time, transmitting the request earlier than the previous asserted request to the downstream unit.

Abstract: The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.

Abstract: A graphics controller includes a memory region configured to store image data for display on a display panel in communication with the graphics controller. Interface circuitry modules where each of the interface circuitry modules is configured to transmit data from the graphics controller over a set of shared data lines are provided. Selection circuitry configured to select data from one of the interface circuitry modules for transmission over the set of shared data lines is included. Line sharing circuitry configured to inform each of the interface circuitry modules to transmit control data is included. The line sharing circuitry is further configured to generate select signals for the selection circuitry. The select signals enable the selection circuitry to select the data from one of the interface circuitry modules for transmission over the shared data lines. A method for driving a display panel and peripheral devices associated with the display panel through common data lines is also provided.

Abstract: A graphics controller includes circuitry for updating multiple display panels over a shared set of data lines associated with the multiple display panels. The circuitry for updating multiple display panels includes circuitry for generating control signals over control lines dedicated to each of the multiple display panels. A memory region configured to store image data for display on the multiple display panels is included with the circuitry for updating multiple display panels. Circuitry configured to select image data associated with one of the multiple display panels for display during an inactive period associated with an other one of the multiple display panels is provided with the circuitry for updating multiple display panels. A method for displaying image data on an RGB panel and a parallel panel simultaneously is also provided.

Abstract: A graphics controller includes an interface for receiving and transmitting image data. A memory region in communication with the interface has a look-up table stored therein. The look-up table is configured to modify color tables which control an amount of data sent to a display screen, wherein the look-up table is programmable to correspond to a power level state of a power supply for the graphics controller. A device and a method for extending battery life for the device are also provided.

Abstract: A graphics controller includes a memory region configured to store image data for display on a display panel in communication with the graphics controller. Interface circuitry modules where each of the interface circuitry modules is configured to transmit data from the graphics controller over a set of shared data lines are provided. Selection circuitry configured to select data from one of the interface circuitry modules for transmission over the set of shared data lines is included. Line sharing circuitry configured to inform each of the interface circuitry modules to transmit control data is included. The line sharing circuitry is further configured to generate select signals for the selection circuitry. The select signals enable the selection circuitry to select the data from one of the interface circuitry modules for transmission over the shared data lines. A method for driving a display panel and peripheral devices associated with the display panel through common data lines is also provided.