Abstract: A switchable folding circuit for an analog-to-digital converter is provided. The switchable folding circuit comprises a plurality of circuit stages wherein each of the circuit stages comprises a differential pair, a current source and a switching unit. The differential pair is connected to the current source via the switching unit and the circuit stages are inversely connected to one another.

Abstract: A cross coupled folding circuit comprises a reference voltage circuit to supply m reference voltages, an amplifier circuit to provide control signals, in response to an input signal and to the reference voltages and 2n?I three times cross coupled folding circuits, each of which comprising three differential transistor pairs, said differential transistors pairs being controlled by said control signals and active in a voltage range around a respective one of said reference voltages, with m=3(2??1). In cascade with said 2n?I folding circuits, there are differential transistor pairs in n?1 successive steps 2n?1, 2n—2, 20. To obtain complete folding, switching circuits are provided, cooperating with the transistor pairs in the last 2n?2 steps of the cascade configuration, to supply the respective control signals to those transistors of the respective differential transistor pairs that provide complete folding.

Abstract: Analog-to-digital converter for converting an analog input signal into a digital binary output signal includes a reference unit for generating a thermometric signal based on comparison of the input signal with a reference voltage level, a first logic circuit connected to the reference unit for generating an intermediate signal based on the thermometric signal, and a second logic circuit connected to the first logic circuit for generating the digital binary output signal based on the intermediate signal. The thermometric signal includes a bit word from a first set of bit words and the intermediate signal includes a bit word from a second set of bit words. Bit words from the second set are arranged in rows of a matrix, the sequence of the rows corresponding to unique numbers represented by the bit words. Respective numbers of bit changes in the respective columns of the matrix are at least substantially equal.

Abstract: A plurality of amplifying circuits having generally uniform amplifying and impedance characteristics, a reference voltage network applying reference voltages of a generally uniformly spacing to each reference voltage terminal of said amplifying circuits, wherein a relative functional position of each amplifying circuit is determined by the magnitude of a received reference voltage; an averaging network, comprising of generally identical averaging impedances coupling output voltage terminals of adjacent amplifying circuits; wherein the amplifying and/or impedance characteristics of said termination circuit and/or the termination reference voltage, and/or the termination averaging impedance are deviant to generate a current in said output voltage terminal of said outer amplifying circuit of said array, that is corrected for the finite size of the array.

Abstract: a plurality of amplifying circuits having generally uniform amplifying and impedance characteristics,