Patents by Inventor Peter Cosmin

Peter Cosmin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scalable electrically eraseable and programmable memory
    Patent number: 8139408
    Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Sorin S. Georgescu, Peter Cosmin, George Smarandoiu
  • Scalable Electrically Eraseable And Programmable Memory
    Publication number: 20080165582
    Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.
    Type: Application
    Filed: March 18, 2008
    Publication date: July 10, 2008
    Applicant: CATALYST SEMICONDUCTOR, INC.
    Inventors: Sorin S. Georgescu, Peter Cosmin, George Smarandoiu