Patents by Inventor Peter Cumming

Peter Cumming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090287859
    Abstract: A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.
    Type: Application
    Filed: May 14, 2009
    Publication date: November 19, 2009
    Inventors: Andrew Bond, Peter Cumming, Colman Hegarty
  • Publication number: 20090273378
    Abstract: A circuit and method for determining the frequency of a first oscillating reference signal generated by a first reference oscillator. The circuit comprises: a second reference oscillator arranged to generate a second oscillating reference signal having a known frequency, a boot memory storing boot code comprising clock configuration code, and a processor coupled to the boot memory and the second reference oscillator. The processor is arranged to execute the boot code from the boot memory upon booting, wherein when executed the clock configuration code operates the processor to determine the frequency of the first reference signal by reference to the second reference signal.
    Type: Application
    Filed: April 23, 2009
    Publication date: November 5, 2009
    Inventors: Jon Mangnall, Peter Cumming
  • Publication number: 20090172380
    Abstract: An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: ICERA INC.
    Inventor: Peter Cumming
  • Publication number: 20090172383
    Abstract: An integrated circuit comprising: a processor; a plurality of external pins operatively coupled to the processor; and a permanently written memory operatively coupled to the processor, the memory having a plurality of regions each storing one or more respective boot properties for booting the processor. The processor is programmed to select one of the regions in dependence on an indication received via one or more of the external pins, to retrieve the one or more respective boot properties from the selected region, and to boot using the one or more retrieved boot properties.
    Type: Application
    Filed: May 27, 2008
    Publication date: July 2, 2009
    Applicant: ICERA INC.
    Inventors: Peter Cumming, Stephen Felix
  • Publication number: 20080000151
    Abstract: A greenhouse comprising a growing section and a climate control system adjacent to the growing section. The climate control system controls the environment within said growing section by flowing ambient air from outside the greenhouse into the growing section, re-circulating air from the growing section back into the growing section, or a combination thereof. A method for controlling the temperature within a greenhouse growing section, comprises flowing air into the growing section from outside the greenhouse to reduce the temperature in the growing section. Warm air is flowed into the growing section to increase the temperature in the growing section, air within the growing section is re-circulated when the temperature therein is at the desired level.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Inventors: Casey Houweling, Peter Cummings
  • Patent number: 7237081
    Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: June 26, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Christian Roussel, Alain Chateau, Peter Cumming
  • Patent number: 7120771
    Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: October 10, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Franck Dahan, Christian Roussel, Alain Chateau, Peter Cumming
  • Patent number: 6781411
    Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: August 24, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Donald E. Steiss, Clive Bittlestone, Peter Cumming, Christopher Barr
  • Publication number: 20030141911
    Abstract: A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.
    Type: Application
    Filed: September 27, 2002
    Publication date: July 31, 2003
    Inventors: Donald E. Steiss, Clive Bittlestone, Peter Cumming, Christopher Barr
  • Publication number: 20030140244
    Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.
    Type: Application
    Filed: September 27, 2002
    Publication date: July 24, 2003
    Inventors: Franck Dahan, Christian Roussel, Alain Chateau, Peter Cumming
  • Publication number: 20030140245
    Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.
    Type: Application
    Filed: September 27, 2002
    Publication date: July 24, 2003
    Inventors: Franck Dahan, Christian Roussel, Alain Chateau, Peter Cumming
  • Publication number: 20030140205
    Abstract: A digital system is provided with a secure mode (3rd level of privilege) built in a non-invasive way on a processor system that includes a processor core, instruction and data caches, a write buffer and a memory management unit. A secure execution mode is thus provided on a platform where the only trusted software is the code stored in ROM. In particular the OS is not trusted, all native applications are not trusted. A secure execution mode is provided that allows virtual addressing when a memory management unit (MMU) is enabled. The secure execution mode allows instruction and data cache to be enabled. A secure execution mode is provided that allows all the system interruptions to be unmasked. The secure mode is entered through a unique entry point. The secure execution mode can be dynamically entered and exited with full hardware assessment of the entry/exit conditions. A specific set of entry conditions is monitored that account for caches, write buffer and MMU being enabled.
    Type: Application
    Filed: September 27, 2002
    Publication date: July 24, 2003
    Inventors: Franck Dahan, Christian Roussel, Alain Chateau, Peter Cumming
  • Patent number: 5978908
    Abstract: A computer instruction supply system has store and fetch circuitry for obtaining a sequence of instructions, test circuitry for locating the first instruction in the sequence to be enabled, and for testing separately successive instructions in the sequence to locate any branch instruction which is predicted to be taken and control circuitry to disregard target addresses of branch instructions in the sequence prior to the first instruction to be executed.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: November 2, 1999
    Assignee: SGS-Thomson Microelectronics Ltd.
    Inventors: Peter Cumming, Richard Grisenthwaite
  • Patent number: 5946705
    Abstract: A cache memory comprises a CAM and a data RAM, the CAM has an associate input and a write input, the associate input being connected to selection circuitry to select write data or associate data so that an associate operation can be effected in parallel with a write operation using the same data to control validation of the write input.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: August 31, 1999
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Peter Cumming, Richard Grisenthwaite
  • Patent number: 5873115
    Abstract: A cache memory has a plurality of cache partitions each having a CAM array, a data RAM and output control circuitry which determines a different priority for each cache partition and permits a cache hit output only from one partition which has the highest priority with a cache hit.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: February 16, 1999
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Peter Cumming, Richard Grisenthwaite
  • Patent number: 5867698
    Abstract: A branch target buffer comprises a partitioned cache memory having for each partition a CAM array holding the least significant bits of a fetch address, a RAM holding the least significant bits of a target address, and comparators for comparing the most significant bits of the fetch and target addresses to control entry of a branch instruction into the buffer.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: February 2, 1999
    Assignee: SGS-Thomas Microelectronics Limited
    Inventors: Peter Cumming, Richard Grisenthwaite
  • Patent number: 4930274
    Abstract: A skylight frame (20) and panel (70) assembly comprises a box-like frame 20 having panel receiving channels (54, 56) for slidably receiving a trough-shaped translucent panel (70) having a downturned flange 74, the frame being receivable in an opening in the roof with a drip molding underlying the roof shingles and overlying the joint line between the frame (20) and roof opening and also covering the exposed joint between the frame (20) and the panel (70).
    Type: Grant
    Filed: January 9, 1989
    Date of Patent: June 5, 1990
    Inventors: Peter A. Cummings, Ronald E. Sears
  • Patent number: 4589239
    Abstract: A skylight assembly for a sloping roof is mounted so that the upper end may be tucked beneath the roof covering so that rain water will drain onto an outer skylight panel; the panel is concave and its lower end extends over the roof covering so that rain water will drain from the panel onto such covering; within and beneath the skylight there is an inner skylight panel mounted for movement to permit ventilation of the room beneath.
    Type: Grant
    Filed: April 30, 1985
    Date of Patent: May 20, 1986
    Inventor: Peter A. Cummings
  • Patent number: RE33720
    Abstract: A skylight assembly for a sloping roof is mounted so that the upper end may be tucked beneath the roof covering so that rain water will drain onto an outer skylight panel; the panel is concave and its lower end extends over the roof covering so that rain water will drain from the panel onto such covering; within and beneath the skylight there is an inner skylight panel mounted for movement to permit ventilation of the room beneath.
    Type: Grant
    Filed: April 5, 1988
    Date of Patent: October 22, 1991
    Inventor: Peter A. Cummings