Patents by Inventor Peter D. Albrecht

Peter D. Albrecht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250026042
    Abstract: A method of slicing wafers from a monocrystalline semiconductor ingot includes attaching a circumferential edge of the ingot to a bond beam and positioning sacrificial disks adjacent longitudinal end faces of the ingot. One sacrificial disk is positioned adjacent each of the longitudinal end faces. The method also includes connecting the bond beam to a wire saw that includes a wire web and performing a slicing operation on the ingot by operating the wire saw to drive the wire web and move the bond beam and the ingot in a movement direction towards the wire web to slice the wafers from the ingot.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Jung-Chiang Liao, Yi-Chun Chou, Liang-Chin Chen, Chin-Yu Chang, Ming-Tao Chia, Peter D. Albrecht
  • Publication number: 20250025951
    Abstract: A system for slicing wafers from a monocrystalline semiconductor ingot includes a wire saw, a bond beam, the monocrystalline semiconductor ingot, and two sacrificial disks. The wire saw includes a wire web and wire guides operable to drive the wire web during a slicing operation. The bond beam is connected to the wire saw. The wire saw is operable to move the bond beam in a movement direction towards the wire web during the slicing operation to slice the wafers from the ingot. The ingot includes longitudinal end faces and a circumferential edge extending between the longitudinal end faces. The ingot is attached to the bond beam along the circumferential edge. One sacrificial disk is positioned adjacent each of the longitudinal end faces of the ingot to inhibit uncontrolled breakage of the wafers during the slicing operation.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Jung-Chiang Liao, Yi-Chun Chou, Liang-Chin Chen, Chin-Yu Chang, Ming-Tao Chia, Peter D. Albrecht
  • Publication number: 20230390962
    Abstract: Systems and methods for controlling the surface profiles of wafers sliced in a wire saw machine. The systems and methods are generally operable to alter the nanotopology of wafers sliced from an ingot by controlling the shape of the wafers. The shape of the wafers is altered for example by changing the temperature of a temperature-controlling fluid circulated in fluid communication with side walls attached to a fixed bearing sidewall of the wire saw.
    Type: Application
    Filed: June 1, 2023
    Publication date: December 7, 2023
    Inventors: Sumeet S. Bhagavat, Carlo Zavattari, Peter D. Albrecht, William L. Luter
  • Patent number: 11764071
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 19, 2023
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 11282715
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 22, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 11276583
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 11276582
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: March 15, 2022
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 10654193
    Abstract: Methods for controlling the surface profiles of wafers sliced from an ingot with a wire saw include measuring an amount of displacement of a sidewall of a frame of the wire saw. The sidewall is connected to a bearing of a wire guide supporting a wire web in the wire saw. Based on the measured amount of displacement of the sidewall, a pressure profile for adjusting a position of the sidewall is determined by a computing device. Pressure is applied to the sidewall using a displacement device according to the determined pressure profile to control the position of the sidewall.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 19, 2020
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Peter D. Albrecht, Carlos Zavattari, Sumeet S. Bhagavat, Vandan Tanna, Uwe Hermes
  • Publication number: 20190333778
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 31, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190311913
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190311912
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190295853
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Publication number: 20190270222
    Abstract: Methods for controlling the surface profiles of wafers sliced from an ingot with a wire saw include measuring an amount of displacement of a sidewall of a frame of the wire saw. The sidewall is connected to a bearing of a wire guide supporting a wire web in the wire saw. Based on the measured amount of displacement of the sidewall, a pressure profile for adjusting a position of the sidewall is determined by a computing device. Pressure is applied to the sidewall using a displacement device according to the determined pressure profile to control the position of the sidewall.
    Type: Application
    Filed: May 16, 2019
    Publication date: September 5, 2019
    Inventors: Peter D. Albrecht, Carlos Zavattari, Sumeet S. Bhagavat, Vandan Tanna, Uwe Hermes
  • Patent number: 10361097
    Abstract: Apparatus for use in preparing heterostructures having a reduced concentration of defects including apparatus for stressing semiconductor substrates to allow them to conform to a crystal having a different crystal lattice constant.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: July 23, 2019
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 10315337
    Abstract: Methods for controlling the surface profiles of wafers sliced from an ingot with a wire saw include measuring an amount of displacement of a sidewall of a frame of the wire saw. The sidewall is connected to a bearing of a wire guide supporting a wire web in the wire saw. The measured amount of displacement of the sidewall is stored as displacement data. Based on the stored data, a pressure profile for adjusting a position of the sidewall is determined by a computing device. Pressure is applied to the sidewall using a displacement device according to the determined pressure profile to control the position of the sidewall.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: June 11, 2019
    Assignee: GlobalWafers Co. Ltd.
    Inventors: Peter D. Albrecht, Carlo Zavattari, Sumeet S. Bhagavat, Vandan Tanna, Uwe Hermes
  • Publication number: 20180056545
    Abstract: Methods for controlling the surface profiles of wafers sliced from an ingot with a wire saw include measuring an amount of displacement of a sidewall of a frame of the wire saw. The sidewall is connected to a bearing of a wire guide supporting a wire web in the wire saw. The measured amount of displacement of the sidewall is stored as displacement data. Based on the stored data, a pressure profile for adjusting a position of the sidewall is determined by a computing device. Pressure is applied to the sidewall using a displacement device according to the determined pressure profile to control the position of the sidewall.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 1, 2018
    Inventors: Peter D. Albrecht, Carlo Zavattari, Sumeet S. Bhagavat, Vandan Tanna, Uwe Hermes
  • Patent number: 9583363
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 9583364
    Abstract: Apparatus and processes for preparing heterostructures with reduced strain are disclosed. The heterostructures may include a semiconductor structure that conforms to a surface layer having a different crystal lattice constant than the structure to form a relatively low-defect heterostructure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 28, 2017
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Robert J. Falster, Vladimir V. Voronkov, John A. Pitney, Peter D. Albrecht
  • Patent number: 9180569
    Abstract: A platen for polishing a surface of a wafer has a reaction plate, a polishing plate, and a bladder. The reaction plate has a top and bottom surface, and defines a longitudinal axis. The polishing plate is positioned coaxially with the reaction plate. The polishing plate has a second top surface and a second bottom surface. The second top surface is adjacent to the bottom surface of the reaction plate. The bladder is coaxially located along a radially outer portion of either the top or bottom surface of the reaction plate. The bladder is connected with the polishing plate and able to expand to deform the polishing plate with respect to the bottom surface of the reaction plate.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: November 10, 2015
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Peter D. Albrecht, Sumeet S. Bhagavat
  • Patent number: 8960657
    Abstract: Systems and methods are disclosed for connecting an ingot to a wire saw with an ingot holder, a bond beam, and a bar. The bar has an angled mating surface that engages a recessed surface formed in a slot of the bond beam. Mechanical fasteners are used to connect the tee bar to the ingot holder. The angle of the mating surface with respect to the recessed surface of the slot prevents deformation of the bond beam and prevents compromising the integrity of the adhesive bond between the ingot and the bond beam.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: February 24, 2015
    Assignee: SunEdison, Inc.
    Inventor: Peter D. Albrecht