Patents by Inventor Peter D. Capofreddi

Peter D. Capofreddi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7224757
    Abstract: A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators 10, each comprising a sequence of three latches 20, 22, 24, connect the modulator's input filter circuit 12 to the modulator's output interfaces 14, providing quantization of the integrated, filtered signal provided by the filter circuit 12. A clock signal having a cycle period Tc enables a first latch 20 connected to the signal input of each comparator 10 to provide a digital signal to the signal input of a second latch 22. The second latch 22 supplies a digital signal to a third latch 24 in the sequence, in response to the signal received from the first latch 20, by a lagged clock signal derived from the given clock signal Tc by providing a first lag time TL where Tc/2?TL>0. A third latch in the sequence is enabled by a clock signal having a second lag time TS=Tc/2+TE, and the delay TE<<Tc/2.
    Type: Grant
    Filed: March 12, 2003
    Date of Patent: May 29, 2007
    Assignee: HRL Laboratories, LLC
    Inventor: Peter D. Capofreddi
  • Publication number: 20030235256
    Abstract: A delta-sigma modulator that provides improved SNR performance in applications such as low-power mobile wireless communications and high frequency radar applications is disclosed. Multiple comparators 10, each comprising a sequence of three latches 20, 22, 24, connect the modulator's input filter circuit 12 to the modulator's output interfaces 14, providing quantization of the integrated, filtered signal provided by the filter circuit 12. A clock signal having a cycle period Tc enables a first latch 20 connected to the signal input of each comparator 10 to provide a digital signal to the signal input of a second latch 22. The second latch 22 supplies a digital signal to a third latch 24 in the sequence, in response to the signal received from the first latch 20, by a lagged clock signal derived from the given clock signal Tc by providing a first lag time TL where Tc/2≧TL>0.
    Type: Application
    Filed: March 12, 2003
    Publication date: December 25, 2003
    Inventor: Peter D. Capofreddi
  • Patent number: 5638071
    Abstract: An error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: June 10, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Peter D. Capofreddi, Edison Fong, Bill C. Wong