Patents by Inventor Peter D. Carleson

Peter D. Carleson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254060
    Abstract: Systems for and methods for generating precise structure reconstruction using slice and view images, are disclosed. An example method comprises, obtaining a slice and view images of a sample that depicts a 3D fiducial and cross-sections of a structure in the sample. The 3D fiducial is configured such that when a layer of material having a uniform thickness is removed from a surface of the sample that includes the 3D fiducial the cross-sectional shape of the 3D fiducial in the new surface is consistent. Relative positions are determined between the 3D fiducial the cross-sections of the structure in individual images. Positional relationships are then determined between the cross-sections of the structure in different images in a common reference frame based on the relative positions.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 11, 2022
    Applicant: FEI Company
    Inventors: Mark NAJARIAN, Victoriea BIRD, Peter D. CARLESON, Sean MORGAN-JONES
  • Patent number: 11171048
    Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 9, 2021
    Assignee: FEI Company
    Inventors: Sean O. Morgan-Jones, Sophia E. Weeks, Peter D. Carleson
  • Publication number: 20210287938
    Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Applicant: FEI Company
    Inventors: Sean O. Morgan-Jones, Sophia E. Weeks, Peter D. Carleson
  • Patent number: 9087366
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. Preferred embodiments of the present invention can also be used to rapidly navigate to one single bit cell in a memory array or similar structure, for example to characterize or correct a defect in that individual bit cell. High-resolution scanning is used to scan only a “strip” of cells on the one edge of the array (along either the X axis or the Y axis) to locate a row containing the desired cell followed by a similar high-speed scan along the located row (in the remaining direction) until the desired cell location is reached. This allows pattern-recognition tools to be used to automatically “count” the cells necessary to navigate to the desired cell, without the large expenditure of time required to image the entire array.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: July 21, 2015
    Assignee: FEI COMPANY
    Inventors: Richard J. Young, Chad Rue, Peter D. Carleson, Reinier Louis Warschauer
  • Publication number: 20150016677
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. Preferred embodiments of the present invention can also be used to rapidly navigate to one single bit cell in a memory array or similar structure, for example to characterize or correct a defect in that individual bit cell. High-resolution scanning is used to scan only a “strip” of cells on the one edge of the array (along either the X axis and the Y axis) to locate a row containing the desired cell followed by a similar high-speed scan along the located row (in the remaining direction) until the desired cell location is reached. This allows pattern-recognition tools to be used to automatically “count” the cells necessary to navigate to the desired cell, without the large expenditure of time required to image the entire array.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 15, 2015
    Applicant: FEI Company
    Inventors: Richard J. Young, Chad Rue, Peter D. Carleson, Reinier Louis Warschauer
  • Patent number: 8781219
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. Preferred embodiments of the present invention can also be used to rapidly navigate to one single bit cell in a memory array or similar structure, for example to characterize or correct a defect in that individual bit cell. High-resolution scanning is used to scan only a “strip” of cells on the one edge of the array (along either the X axis and the Y axis) to locate a row containing the desired cell followed by a similar high-speed scan along the located row (in the remaining direction) until the desired cell location is reached. This allows pattern-recognition tools to be used to automatically “count” the cells necessary to navigate to the desired cell, without the large expenditure of time required to image the entire array.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: July 15, 2014
    Assignee: FEI Company
    Inventors: Reinier Louis Warschauer, Richard J. Young, Chad Rue, Peter D. Carleson
  • Patent number: 8358832
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. This invention demonstrates a method where high accuracy navigation to the site of interest within a relatively large local area (e.g. an area 200 ?m×200 ?m) is possible even where the stage/navigation system is not normally capable of such high accuracy navigation. The combination of large area, high-resolution scanning, digital zoom and registration of the image to an idealized coordinate system enables navigation around a local area without relying on stage movements. Once the image is acquired any sample or beam drift will not affect the alignment. Preferred embodiments thus allow accurate navigation to a site on a sample with sub-100 nm accuracy, even without a high-accuracy stage/navigation system.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: January 22, 2013
    Assignee: FEI Company
    Inventors: Richard J. Young, Chad Rue, Peter D Carleson
  • Publication number: 20120328151
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. Preferred embodiments of the present invention can also be used to rapidly navigate to one single bit cell in a memory array or similar structure, for example to characterize or correct a defect in that individual bit cell. High-resolution scanning is used to scan only a “strip” of cells on the one edge of the array (along either the X axis and the Y axis) to locate a row containing the desired cell followed by a similar high-speed scan along the located row (in the remaining direction) until the desired cell location is reached. This allows pattern-recognition tools to be used to automatically “count” the cells necessary to navigate to the desired cell, without the large expenditure of time required to image the entire array.
    Type: Application
    Filed: May 25, 2012
    Publication date: December 27, 2012
    Applicant: FEI COMPANY
    Inventors: Reinier Louis Warschauer, Richard J. Young, Chad Rue, Peter D. Carleson
  • Publication number: 20120045097
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. This invention demonstrates a method where high accuracy navigation to the site of interest within a relatively large local area (e.g. an area 200 ?m×200 ?m) is possible even where the stage/navigation system is not normally capable of such high accuracy navigation. The combination of large area, high-resolution scanning, digital zoom and registration of the image to an idealized coordinate system enables navigation around a local area without relying on stage movements. Once the image is acquired any sample or beam drift will not affect the alignment. Preferred embodiments thus allow accurate navigation to a site on a sample with sub-100 nm accuracy, even without a high-accuracy stage/navigation system.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 23, 2012
    Applicant: FEI COMPANY
    Inventors: RICHARD J. YOUNG, CHAD RUE, PETER D. CARLESON
  • Patent number: 8059918
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. This invention demonstrates a method where high accuracy navigation to the site of interest within a relatively large local area (e.g. an area 200 ?m×200 ?m) is possible even where the stage/navigation system is not normally capable of such high accuracy navigation. The combination of large area, high-resolution scanning, digital zoom and registration of the image to an idealized coordinate system enables navigation around a local area without relying on stage movements. Once the image is acquired any sample or beam drift will not affect the alignment. Preferred embodiments thus allow accurate navigation to a site on a sample with sub-100 nm accuracy, even without a high-accuracy stage/navigation system.
    Type: Grant
    Filed: October 11, 2009
    Date of Patent: November 15, 2011
    Assignee: FEI Company
    Inventors: Richard J. Young, Chad Rue, Peter D. Carleson
  • Publication number: 20100092070
    Abstract: An improved method of high accuracy beam placement for local area navigation in the field of semiconductor chip manufacturing. This invention demonstrates a method where high accuracy navigation to the site of interest within a relatively large local area (e.g. an area 200 ?m×200 ?m) is possible even where the stage/navigation system is not normally capable of such high accuracy navigation. The combination of large area, high-resolution scanning, digital zoom and registration of the image to an idealized coordinate system enables navigation around a local area without relying on stage movements. Once the image is acquired any sample or beam drift will not affect the alignment. Preferred embodiments thus allow accurate navigation to a site on a sample with sub-100 nm accuracy, even without a high-accuracy stage/navigation system.
    Type: Application
    Filed: October 11, 2009
    Publication date: April 15, 2010
    Applicant: FEI COMPANY
    Inventors: RICHARD J. YOUNG, Chad Rue, Peter D. Carleson
  • Patent number: 7388218
    Abstract: A method of navigating or endpointing a microscopic structure by subsurface imaging using a beam of electrons having sufficient energy to penetrate the surface and produce a subsurface image. For endpointing, when the subsurface image become relatively clear at a known electron energy, a user knows that he is approaching the buried feature. For navigating, a subsurface image can be formed of fiducials or other features to determine the position of the beam on the device.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: June 17, 2008
    Assignee: FEI Company
    Inventor: Peter D. Carleson