Abstract: A computing system includes an application configured to request execution of at least one translation including at least one command. A first coupling facility is configured to perform a first modification process to modify a first structure based on a received command associated with an ongoing transaction. A second coupling facility includes a secondary circular queue loaded with first data blocks indicating the first modification process, and is configured to output a message response block (MRB). The application determines a most recent modification process performed by the secondary coupling facility based on the MRB.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A computing system includes an application configured to request execution of at least one translation including at least one command. A first coupling facility is configured to perform a first modification process to modify a first structure based on a received command associated with an ongoing transaction. A second coupling facility includes a secondary circular queue loaded with first data blocks indicating the first modification process, and is configured to output a message response block (MRB). The application determines a most recent modification process performed by the secondary coupling facility based on the MRB.

Abstract: Examples of techniques for processor mode switching are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method for processor mode switching to cause a processing system to switch a mode of a processor of a plurality of processors, wherein each processor of the plurality of processors is one of an active processor or an inactive processor, and wherein each active processor is in one of a first mode and a second mode may include: setting a processor threshold; determining whether a number of active processors exceeds the processor threshold; and responsive to determining that the number of active processors exceeds the processor threshold, switching the mode of the processor from the first mode to the second mode.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A computing system includes an application configured to request execution of at least one translation including at least one command. A first coupling facility is configured to perform a first modification process to modify a first structure based on a received command associated with an ongoing transaction. A second coupling facility includes a secondary circular queue loaded with first data blocks indicating the first modification process, and is configured to output a message response block (MRB). The application determines a most recent modification process performed by the secondary coupling facility based on the MRB.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A computing system is configured to maintain equivalency of independent queues located in different coupling facilities. The computer system includes a first coupling facility and a second coupling facility. The first coupling facility receives a plurality of different commands instructing the first coupling facility to load data into a first structure. The first coupling facility generates a first command data block including first data corresponding to a received first command and a first sequence value indicating a sequence at which the first data was loaded into the first structure with respect to remaining data corresponding to the plurality of commands. A second coupling facility includes a second structure and a second queue. The second coupling facility receives the first command data block from a first queue of the first coupling facility and loads the first data from the second queue into the second structure based on the first sequence value.

Abstract: A computing system is configured to maintain equivalency of independent structures located in different coupling facilities. The computing system includes a first coupling facility and a second coupling facility different from the first coupling facility. The first coupling facility includes a first structure that receives a first data modification based on a modification command requested by an application executed by an operating system. The second coupling facility in signal communication with the first coupling facility and includes a secondary structure that receives a second data modification based on the first data modification applied to the first structure. The first coupling facility outputs a Push List Structure Object (PLSO) command data block to the second coupling facility. The PLSO command data block indicates the first data modification applied to the first structure.

Abstract: Examples of techniques for processor mode switching are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method for processor mode switching to cause a processing system to switch a mode of a processor of a plurality of processors, wherein each processor of the plurality of processors is one of an active processor or an inactive processor, and wherein each active processor is in one of a first mode and a second mode may include: setting a processor threshold; determining whether a number of active processors exceeds the processor threshold; and responsive to determining that the number of active processors exceeds the processor threshold, switching the mode of the processor from the first mode to the second mode.

Abstract: Examples of techniques for fast task dispatching using a dispatching processor are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: analyzing, based on a list of resources maintained by a dispatcher processor, a task from a suspended queue to determine whether the task is waiting for a resource in order to execute; determining whether the task is waiting for a resource in order to execute; responsive to determining that the task is not waiting for the resource in order to execute, placing the task on a ready queue and adding an address of the resource to the list of resources maintained by the dispatcher processor; and dispatching the task to one of a plurality of execution processors for execution.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A computing system is configured to maintain equivalency of independent structures located in different coupling facilities. The computing system includes a first coupling facility and a second coupling facility different from the first coupling facility. The first coupling facility includes a first structure that receives a first data modification based on a modification command requested by an application executed by an operating system. The second coupling facility in signal communication with the first coupling facility and includes a secondary structure that receives a second data modification based on the first data modification applied to the first structure. The first coupling facility outputs a Push List Structure Object (PLSO) command data block to the second coupling facility. The PLSO command data block indicates the first data modification applied to the first structure.

Abstract: A computing system is configured to maintain equivalency of independent queues located in different coupling facilities. The computer system includes a first coupling facility and a second coupling facility. The first coupling facility receives a plurality of different commands instructing the first coupling facility to load data into a first structure. The first coupling facility generates a first command data block including first data corresponding to a received first command and a first sequence value indicating a sequence at which the first data was loaded into the first structure with respect to remaining data corresponding to the plurality of commands. A second coupling facility includes a second structure and a second queue. The second coupling facility receives the first command data block from a first queue of the first coupling facility and loads the first data from the second queue into the second structure based on the first sequence value.

Abstract: A computing system includes an application configured to request execution of at least one translation including at least one command. A first coupling facility is configured to perform a first modification process to modify a first structure based on a received command associated with an ongoing transaction. A second coupling facility includes a secondary circular queue loaded with first data blocks indicating the first modification process, and is configured to output a message response block (MRB). The application determines a most recent modification process performed by the secondary coupling facility based on the MRB.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A computer-implemented method for operating multiple processors is described. The method includes receiving, by a processor operatively connected to a data channel, work task data that includes execution instructions, and storing, with the processor, the work task data to an operatively connected memory storage area. The method further includes updating a sequential work buffer indicative of whether the work task data is a highest current value in a plurality of sequential execution values, performing a compare double swap (CDS) lock attempt, and executing, with the processor, the work task data responsive to a successful lock attempt.

Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.

Abstract: A system and method for correlating asynchronous operations via an operation identifier comprises receiving an originating operation from a first system that indicates a change in the first system and generating a first message with respect to the originating operation. The first message is associated with the operation identifier. The system and method further propagates the first message to a second system, which causes a subsequent operation being associated with the operation identifier to be performed by the second system, and correlates the originating operation and the subsequent operation via the operation identifier.

Abstract: A system and method for correlating asynchronous operations via an operation identifier comprises receiving an originating operation from a first system that indicates a change in the first system and generating a first message with respect to the originating operation. The first message is associated with the operation identifier. The system and method further propagates the first message to a second system, which causes a subsequent operation being associated with the operation identifier to be performed by the second system, and correlates the originating operation and the subsequent operation via the operation identifier.