Abstract: A network device, also referred to as the Compression Enhanced Network Processor (CENP), with embedded parallel (or fast serial) compression and/or decompression capability. The network device may be a network processor based multi-ported switch, bridge, router, hub, or other device. The CENP may provide improved data density, efficiency and bandwidth for each port of a multi-port network switch. In one embodiment, the CENP may comprise a network processor core, a memory management unit, a memory buffer (e.g., an SRAM memory buffer), and a system memory. The CENP may comprise a compression and decompression engine. In one embodiment, the memory management unit comprises the compression and decompression engine, and thus may be referred to as a Compression Enhanced Memory Controller Unit (CEMCU).

Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of data compression engines each implementing a different data compression algorithm. A codec system may be designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. Uncompressed data may be compressed using a plurality of compression engines in parallel, with each engine compressing the data using a different lossless data compression algorithm. At least one of the data compression engines may implement a parallel lossless data compression algorithm designed to process stream data at more than a single byte or symbol at one time. The plurality of different versions of compressed data generated by the different compression algorithms may be examined to determine an optimal version of the compressed data according to one or more predetermined criteria. A codec system may be integrated in a processor, a system memory controller or elsewhere within a system.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of parallel data compression and/or parallel data decompression engines designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. The plurality of compression/decompression engines may each implement a parallel lossless data compression/decompression algorithm. The codec system may split incoming uncompressed or compressed data up among the plurality of compression/decompression engines. Each of the plurality of compression/decompression engines may compress or decompress a particular part of the data. The codec system may then merge the portions of compressed or uncompressed data output from the plurality of compression/decompression engines. The codec system may implement a method for performing parallel data compression and/or decompression designed to process stream data at more than a single byte or symbol at one time.

Abstract: A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs.

Abstract: A system and method for managing a functional unit in a system using a data movement engine. An exemplary system may comprise a CPU coupled to a memory controller. The memory controller may include or couple to a data movement engine (DME). The memory controller may in turn couple to a system memory or other device which includes at least one functional unit. The DME may operate to transfer data to/from the system memory and/or the functional unit, as described herein. In one embodiment, the DME may also include multiple DME channels or multiple DME contexts. The DME may operate to direct the functional unit to perform operations on data in the system memory. For example, the DME may read source data from the system memory, the DME may then write the source data to the functional unit, the functional unit may operate on the data to produce modified data, the DME may then read the modified data from the functional unit, and the DME may then write the modified data to a destination in the system memory.

Abstract: A network device, also referred to as the Compression Enhanced Network Processor (CENP), with embedded parallel (or fast serial) compression and/or decompression capability. The network device may be a network processor based multi-ported switch, bridge, router, hub, or other device. The CENP may provide improved data density, efficiency and bandwidth for each port of a multi-port network switch. In one embodiment, the CENP may comprise a network processor core, a memory management unit, a memory buffer (e.g., an SRAM memory buffer), and a system memory. The CENP may comprise a compression and decompression engine. In one embodiment, the memory management unit comprises the compression and decompression engine, and thus may be referred to as a Compression Enhanced Memory Controller Unit (CEMCU).

Abstract: A spanning based method for rendering and display of 3D graphical data on a display device. The method first parses the geometry data, generates independent vertex-sorted geometric primitives (e.g., triangles) and then performs setup on the geometric primitives. The method then computes horizontal segments that make up each triangle, performs a Y sort of the triangles for each span line, and performs an X sort of triangle segments and vertices for each span line. The method then performs a Z rules determination for each span line to discard or reject hidden segments. The method then constructs the 3-D VDRL list for each span line comprising pointers which reference viewed triangle spans. During execution, the 3-D VDRL is read and interpreted to generate pixel data. The pixel data includes the viewed triangle spans and may include texture data or other data referenced by the VDRL.

Abstract: A video/graphics controller (IMC) which includes a novel spanning based method for rendering and display of 3D graphical data on a display device. The IMC first operates to construct a 3-D Virtual display refresh list (3D-VDRL) in memory. The IMC constructs the 3-D VDRL by first parsing the geometry data, generating independent vertex-sorted geometric primitives (e.g., triangles) and then performing setup on the geometric primitives. Setup includes assembling a list of parameters for each of the triangle vertices and determining slope values for the triangle edges. The IMC uses 3D vertex and slope information to compute horizontal segments that make up each triangle. The IMC then performs a Y sort of the triangles for each span line, and an X sort of triangles segments and vertices for each span line. For each span line, triangle segments are generated and X sorted based on starting X position of triangles for each segment.

Abstract: A graphics controller which performs display list-based video refresh operations that enable objects with independent frame rates to be efficiently assembled is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller also creates, maintains, and deletes draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs.

Abstract: A graphics controller which performs display list-based video refresh operations and compresses assembled scan lines or portions thereof is disclosed. The graphics controller maintains a virtual display refresh list (VDRL) comprising a plurality of pointers to scan line segments in memory. The graphics controller may also create, maintain, and delete draw display lists (DDLs) that comprise pointers to object display list subroutines (ODLs) that independently draw objects in memory. The ODLs may allocated one or more buffers in memory into which different frames of the objects are drawn. When an ODL has completed executing, the corresponding pointer in the DDL may be updated to point to the buffer location in memory that stores the newly completed object frame. The VDRL is maintained independently (and may be doubled-buffered) and is updated using the DDLs. The video data assembled as the VDRL is executed is output to the display device. The video data may also be compressed and stored into memory.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of data compression engines each implementing a different data compression algorithm. A codec system may be designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. Uncompressed data may be compressed using a plurality of compression engines in parallel, with each engine compressing the data using a different lossless data compression algorithm. At least one of the data compression engines may implement a parallel lossless data compression algorithm designed to process stream data at more than a single byte or symbol at one time. The plurality of different versions of compressed data generated by the different compression algorithms may be examined to determine an optimal version of the compressed data according to one or more predetermined criteria. A codec system may be integrated in a processor, a system memory controller or elsewhere within a system.

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of parallel data compression and/or parallel data decompression engines designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. The plurality of compression/decompression engines may each implement a parallel lossless data compression/decompression algorithm. The codec system may split incoming uncompressed or compressed data up among the plurality of compression/decompression engines. Each of the plurality of compression/decompression engines may compress or decompress a particular part of the data. The codec system may then merge the portions of compressed or uncompressed data output from the plurality of compression/decompression engines. The codec system may implement a method for performing parallel data compression and/or decompression designed to process stream data at more than a single byte or symbol at one time.

Abstract: A system is described for selectively configuring a backplane-based SCSI subsystem in at least two alternative drive configurations. A concatenator/splitter (C/S) device enables a user to concatenate several SCSI devices onto a single bus, or alternatively to split the devices onto multiple buses. In either configuration, the bus or buses are properly terminated. The C/S device is located on the backplane between two buses and is connected to each bus by a connector section. A removable interface module plugs into the connector section in either an upright or upside-down orientation, as selected by the user, to choose either a concatenated or split bus configuration. A terminating network is included in the interface module in order to terminate the first bus when the subsystem is configured in the split bus arrangement.